Lines Matching +full:5 +full:ns
42 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
43 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
44 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
100 #define V_MCFG_CASWIDTH(caswidth) (((caswidth)-5) << 20) /* 20:22 */
111 /* Hynix part of Overo (165MHz optimized) 6.06ns */
163 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
189 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
209 #define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
226 /* Micron part (200MHz optimized) 5 ns */
252 /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
253 #define SAMSUNG_TDAL_165 5
271 #define SAMSUNG_TXP_165 5
295 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
324 /* NUMONYX part of IGEP v2 (200MHz optimized) 5 ns */
326 /* 15/5 + 15/5 = 3 + 3 -> 6 */
327 #define NUMONYX_TDPL_200 3 /* 15/5 = 3 -> 3 (Twr) */
328 #define NUMONYX_TRRD_200 2 /* 10/5 = 2 */
329 #define NUMONYX_TRCD_200 4 /* 16.2/5 = 3.24 -> 4 */
330 #define NUMONYX_TRP_200 3 /* 15/5 = 3 */
331 #define NUMONYX_TRAS_200 8 /* 40/5 = 8 */
332 #define NUMONYX_TRC_200 11 /* 55/5 = 11 */
333 #define NUMONYX_TRFC_200 28 /* 140/5 = 28 */