Lines Matching +full:0 +full:x00000031
12 #define CS0 0x0
13 #define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
17 STACKED = 0,
33 #define SDRC_SHARING 0x00000100
34 #define SDRC_MR_0_SDR 0x00000031
38 * enable at bits 0:1 and an autorefresh counter value in bits 8:23. The
41 #define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01
42 #define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
43 #define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
44 #define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
46 #define DLL_OFFSET 0
49 #define DLL_LOCKDLL 0
50 #define DLL_DLLPHASE_72 0
58 #define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
59 #define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
60 #define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
61 #define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
62 #define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
63 #define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
64 #define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
65 #define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
78 #define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
79 #define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
80 #define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
81 #define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
94 #define V_MCFG_RAMTYPE_DDR (0x1)
95 #define V_MCFG_DEEPPD_EN (0x1 << 3)
96 #define V_MCFG_B32NOT16_32 (0x1 << 4)
97 #define V_MCFG_BANKALLOCATION_RBC (0x2 << 6) /* 6:7 */
99 #define V_MCFG_ADDRMUXLEGACY_FLEX (0x1 << 19)
218 #define MICRON_BL_165 0x2
219 #define MICRON_SIL_165 0x0
220 #define MICRON_CASL_165 0x3
221 #define MICRON_WBST_165 0x0
285 #define SAMSUNG_BL_165 0x2
286 #define SAMSUNG_SIL_165 0x0
287 #define SAMSUNG_CASL_165 0x3
288 #define SAMSUNG_WBST_165 0x0
293 #define SAMSUNG_SHARING 0x00003700
383 * GPMC_SIZE_128M - 0x8
384 * GPMC_SIZE_64M - 0xC
385 * GPMC_SIZE_32M - 0xE
386 * GPMC_SIZE_16M - 0xF
390 #define GPMC_SIZE_256M 0x0
391 #define GPMC_SIZE_128M 0x8
392 #define GPMC_SIZE_64M 0xC
393 #define GPMC_SIZE_32M 0xE
394 #define GPMC_SIZE_16M 0xF
396 #define GPMC_BASEADDR_MASK 0x3F
398 #define GPMC_CS_ENABLE 0x1
400 #define M_NAND_GPMC_CONFIG1 0x00001800
401 #define M_NAND_GPMC_CONFIG2 0x00141400
402 #define M_NAND_GPMC_CONFIG3 0x00141400
403 #define M_NAND_GPMC_CONFIG4 0x0F010F01
404 #define M_NAND_GPMC_CONFIG5 0x010C1414
405 #define M_NAND_GPMC_CONFIG6 0x1f0f0A80
406 #define M_NAND_GPMC_CONFIG7 0x00000C44
408 #define STNOR_GPMC_CONFIG1 0x3
409 #define STNOR_GPMC_CONFIG2 0x00151501
410 #define STNOR_GPMC_CONFIG3 0x00060602
411 #define STNOR_GPMC_CONFIG4 0x11091109
412 #define STNOR_GPMC_CONFIG5 0x01141F1F
413 #define STNOR_GPMC_CONFIG6 0x000004c4
415 #define SIBNOR_GPMC_CONFIG1 0x1200
416 #define SIBNOR_GPMC_CONFIG2 0x001f1f00
417 #define SIBNOR_GPMC_CONFIG3 0x00080802
418 #define SIBNOR_GPMC_CONFIG4 0x1C091C09
419 #define SIBNOR_GPMC_CONFIG5 0x01131F1F
420 #define SIBNOR_GPMC_CONFIG6 0x1F0F03C2
422 #define SDPV2_MPDB_GPMC_CONFIG1 0x00611200
423 #define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01
424 #define SDPV2_MPDB_GPMC_CONFIG3 0x00080803
425 #define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09
426 #define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F
427 #define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4
429 #define MPDB_GPMC_CONFIG1 0x00011000
430 #define MPDB_GPMC_CONFIG2 0x001f1f01
431 #define MPDB_GPMC_CONFIG3 0x00080803
432 #define MPDB_GPMC_CONFIG4 0x1c0b1c0a
433 #define MPDB_GPMC_CONFIG5 0x041f1F1F
434 #define MPDB_GPMC_CONFIG6 0x1F0F04C4
436 #define P2_GPMC_CONFIG1 0x0
437 #define P2_GPMC_CONFIG2 0x0
438 #define P2_GPMC_CONFIG3 0x0
439 #define P2_GPMC_CONFIG4 0x0
440 #define P2_GPMC_CONFIG5 0x0
441 #define P2_GPMC_CONFIG6 0x0
443 #define ONENAND_GPMC_CONFIG1 0x00001200
444 #define ONENAND_GPMC_CONFIG2 0x000F0F01
445 #define ONENAND_GPMC_CONFIG3 0x00030301
446 #define ONENAND_GPMC_CONFIG4 0x0F040F04
447 #define ONENAND_GPMC_CONFIG5 0x010F1010
448 #define ONENAND_GPMC_CONFIG6 0x1F060000
450 #define NET_GPMC_CONFIG1 0x00001000
451 #define NET_GPMC_CONFIG2 0x001e1e01
452 #define NET_GPMC_CONFIG3 0x00080300
453 #define NET_GPMC_CONFIG4 0x1c091c09
454 #define NET_GPMC_CONFIG5 0x04181f1f
455 #define NET_GPMC_CONFIG6 0x00000FCF
456 #define NET_GPMC_CONFIG7 0x00000f6c
459 #define NET_LAN9221_GPMC_CONFIG1 0x00001000
460 #define NET_LAN9221_GPMC_CONFIG2 0x00060700
461 #define NET_LAN9221_GPMC_CONFIG3 0x00020201
462 #define NET_LAN9221_GPMC_CONFIG4 0x06000700
463 #define NET_LAN9221_GPMC_CONFIG5 0x0006090A
464 #define NET_LAN9221_GPMC_CONFIG6 0x87030000
465 #define NET_LAN9221_GPMC_CONFIG7 0x00000f6c