Lines Matching +full:0 +full:x3
20 mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */
24 mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
25 mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
26 mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
27 mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
28 mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
29 mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
30 mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
31 mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
32 mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
33 mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
34 mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
35 mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
36 mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
37 mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
41 mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */
42 mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */
43 mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */
44 mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */
45 mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */
46 mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */
47 mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */
48 mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */
49 mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */
50 mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */
51 mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
52 mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
53 mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
54 mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
55 mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
56 mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
57 mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */
58 mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */
59 mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */
60 mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */
64 mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */
65 mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */
66 mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */
67 mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */
68 mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */
69 mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */
70 mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */
74 mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */
75 mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */
76 mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */
77 mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */
78 mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */
82 mxs_reg_32(hw_pinctrl_din0) /* 0x900 */
83 mxs_reg_32(hw_pinctrl_din1) /* 0x910 */
84 mxs_reg_32(hw_pinctrl_din2) /* 0x920 */
85 mxs_reg_32(hw_pinctrl_din3) /* 0x930 */
86 mxs_reg_32(hw_pinctrl_din4) /* 0x940 */
90 mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */
91 mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */
92 mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */
93 mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */
94 mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */
98 mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
99 mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
100 mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
101 mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
102 mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
106 mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
107 mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
108 mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
109 mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
110 mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
114 mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
115 mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
116 mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
117 mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
118 mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
122 mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
123 mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
124 mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
125 mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
126 mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
130 mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
131 mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
132 mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
133 mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
134 mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
138 mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
142 mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
157 #define PINCTRL_CTRL_IRQOUT0 (1 << 0)
159 #define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14)
161 #define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12)
163 #define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10)
165 #define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8)
167 #define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6)
169 #define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4)
171 #define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2)
173 #define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0)
174 #define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0
176 #define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24)
178 #define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22)
180 #define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20)
182 #define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18)
184 #define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16)
186 #define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14)
188 #define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12)
190 #define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10)
192 #define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8)
194 #define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6)
196 #define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4)
198 #define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2)
200 #define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0)
201 #define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0
203 #define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30)
205 #define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28)
207 #define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26)
209 #define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24)
211 #define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22)
213 #define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20)
215 #define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18)
217 #define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16)
219 #define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14)
221 #define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12)
223 #define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10)
225 #define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8)
227 #define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6)
229 #define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4)
231 #define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2)
233 #define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0)
234 #define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0
236 #define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30)
238 #define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28)
240 #define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26)
242 #define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24)
244 #define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22)
246 #define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20)
248 #define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18)
250 #define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16)
252 #define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14)
254 #define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12)
256 #define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10)
258 #define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8)
260 #define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6)
262 #define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4)
264 #define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2)
266 #define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0)
267 #define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0
269 #define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30)
271 #define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28)
273 #define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26)
275 #define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24)
277 #define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20)
279 #define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18)
281 #define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16)
283 #define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14)
285 #define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12)
287 #define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10)
289 #define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8)
291 #define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6)
293 #define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4)
295 #define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2)
297 #define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0)
298 #define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0
300 #define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22)
302 #define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20)
304 #define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18)
306 #define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16)
308 #define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10)
310 #define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8)
312 #define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6)
314 #define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4)
316 #define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2)
318 #define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0)
319 #define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0
321 #define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30)
323 #define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28)
325 #define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26)
327 #define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24)
329 #define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22)
331 #define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20)
333 #define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18)
335 #define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16)
337 #define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14)
339 #define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12)
341 #define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10)
343 #define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8)
345 #define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6)
347 #define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4)
349 #define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2)
351 #define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0)
352 #define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0
354 #define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28)
356 #define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26)
358 #define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24)
360 #define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22)
362 #define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20)
364 #define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18)
366 #define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16)
368 #define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14)
370 #define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12)
372 #define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10)
374 #define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8)
376 #define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4)
378 #define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2)
380 #define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0)
381 #define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0
383 #define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30)
385 #define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28)
387 #define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26)
389 #define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24)
391 #define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22)
393 #define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20)
395 #define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18)
397 #define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16)
399 #define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14)
401 #define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12)
403 #define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10)
405 #define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8)
407 #define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6)
409 #define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4)
411 #define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2)
413 #define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0)
414 #define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0
416 #define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8)
418 #define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0)
419 #define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0
421 #define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30)
423 #define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28)
425 #define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26)
427 #define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24)
429 #define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22)
431 #define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20)
433 #define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18)
435 #define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16)
437 #define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14)
439 #define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12)
441 #define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10)
443 #define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8)
445 #define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6)
447 #define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4)
449 #define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2)
451 #define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0)
452 #define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0
454 #define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20)
456 #define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14)
458 #define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12)
460 #define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10)
462 #define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8)
464 #define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6)
466 #define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4)
468 #define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2)
470 #define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0)
471 #define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0
473 #define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28)
475 #define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26)
477 #define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24)
479 #define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22)
481 #define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20)
483 #define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18)
485 #define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16)
487 #define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14)
489 #define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12)
491 #define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10)
493 #define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8)
495 #define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6)
497 #define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4)
499 #define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2)
501 #define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0)
502 #define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0
504 #define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16)
506 #define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14)
508 #define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12)
510 #define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10)
512 #define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8)
514 #define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6)
516 #define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4)
518 #define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2)
520 #define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0)
521 #define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0
524 #define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28)
527 #define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24)
530 #define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20)
533 #define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16)
536 #define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12)
539 #define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8)
542 #define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4)
545 #define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0)
546 #define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0
549 #define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28)
552 #define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24)
555 #define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20)
558 #define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16)
561 #define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12)
564 #define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8)
567 #define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4)
570 #define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0)
571 #define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0
574 #define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16)
577 #define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12)
580 #define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8)
583 #define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4)
586 #define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0)
587 #define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0
590 #define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28)
593 #define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24)
596 #define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20)
599 #define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16)
602 #define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12)
605 #define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8)
608 #define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4)
611 #define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0)
612 #define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0
615 #define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28)
618 #define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24)
621 #define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20)
624 #define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16)
627 #define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12)
630 #define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8)
633 #define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4)
636 #define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0)
637 #define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0
640 #define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28)
643 #define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24)
646 #define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20)
649 #define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16)
652 #define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12)
655 #define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8)
658 #define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4)
661 #define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0)
662 #define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0
665 #define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28)
668 #define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24)
671 #define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20)
674 #define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16)
677 #define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12)
680 #define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8)
683 #define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4)
686 #define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0)
687 #define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0
690 #define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28)
693 #define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24)
696 #define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20)
699 #define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16)
702 #define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12)
705 #define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8)
708 #define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4)
711 #define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0)
712 #define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0
715 #define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28)
718 #define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24)
721 #define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20)
724 #define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16)
727 #define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8)
730 #define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4)
733 #define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0)
734 #define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0
737 #define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20)
740 #define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16)
743 #define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12)
746 #define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8)
749 #define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4)
752 #define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0)
753 #define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0
756 #define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12)
759 #define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8)
762 #define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4)
765 #define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0)
766 #define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0
769 #define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28)
772 #define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24)
775 #define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20)
778 #define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16)
781 #define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12)
784 #define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8)
787 #define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4)
790 #define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0)
791 #define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0
794 #define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28)
797 #define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24)
800 #define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20)
803 #define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16)
806 #define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12)
809 #define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8)
812 #define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4)
815 #define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0)
816 #define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0
819 #define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28)
822 #define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24)
825 #define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20)
828 #define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16)
831 #define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8)
834 #define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4)
837 #define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0)
838 #define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0
841 #define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24)
844 #define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20)
847 #define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16)
850 #define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12)
853 #define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8)
856 #define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4)
859 #define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0)
860 #define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0
863 #define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28)
866 #define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24)
869 #define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20)
872 #define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16)
875 #define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12)
878 #define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8)
881 #define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4)
884 #define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0)
885 #define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0
888 #define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28)
891 #define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24)
894 #define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20)
897 #define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16)
900 #define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12)
903 #define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8)
906 #define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4)
909 #define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0)
910 #define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0
913 #define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16)
916 #define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0)
917 #define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0
939 #define PINCTRL_PULL0_BANK0_PIN00 (1 << 0)
972 #define PINCTRL_PULL1_BANK1_PIN00 (1 << 0)
998 #define PINCTRL_PULL2_BANK2_PIN00 (1 << 0)
1029 #define PINCTRL_PULL3_BANK3_PIN00 (1 << 0)
1048 #define PINCTRL_PULL4_BANK4_PIN00 (1 << 0)
1074 #define PINCTRL_PULL5_BANK5_PIN00 (1 << 0)
1099 #define PINCTRL_PULL6_BANK6_PIN00 (1 << 0)
1101 #define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff
1102 #define PINCTRL_DOUT0_DOUT_OFFSET 0
1104 #define PINCTRL_DOUT1_DOUT_MASK 0xffffffff
1105 #define PINCTRL_DOUT1_DOUT_OFFSET 0
1107 #define PINCTRL_DOUT2_DOUT_MASK 0xfffffff
1108 #define PINCTRL_DOUT2_DOUT_OFFSET 0
1110 #define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff
1111 #define PINCTRL_DOUT3_DOUT_OFFSET 0
1113 #define PINCTRL_DOUT4_DOUT_MASK 0x1fffff
1114 #define PINCTRL_DOUT4_DOUT_OFFSET 0
1116 #define PINCTRL_DIN0_DIN_MASK 0x1fffffff
1117 #define PINCTRL_DIN0_DIN_OFFSET 0
1119 #define PINCTRL_DIN1_DIN_MASK 0xffffffff
1120 #define PINCTRL_DIN1_DIN_OFFSET 0
1122 #define PINCTRL_DIN2_DIN_MASK 0xfffffff
1123 #define PINCTRL_DIN2_DIN_OFFSET 0
1125 #define PINCTRL_DIN3_DIN_MASK 0x7fffffff
1126 #define PINCTRL_DIN3_DIN_OFFSET 0
1128 #define PINCTRL_DIN4_DIN_MASK 0x1fffff
1129 #define PINCTRL_DIN4_DIN_OFFSET 0
1131 #define PINCTRL_DOE0_DOE_MASK 0x1fffffff
1132 #define PINCTRL_DOE0_DOE_OFFSET 0
1134 #define PINCTRL_DOE1_DOE_MASK 0xffffffff
1135 #define PINCTRL_DOE1_DOE_OFFSET 0
1137 #define PINCTRL_DOE2_DOE_MASK 0xfffffff
1138 #define PINCTRL_DOE2_DOE_OFFSET 0
1140 #define PINCTRL_DOE3_DOE_MASK 0x7fffffff
1141 #define PINCTRL_DOE3_DOE_OFFSET 0
1143 #define PINCTRL_DOE4_DOE_MASK 0x1fffff
1144 #define PINCTRL_DOE4_DOE_OFFSET 0
1146 #define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff
1147 #define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0
1149 #define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff
1150 #define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0
1152 #define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff
1153 #define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0
1155 #define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff
1156 #define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0
1158 #define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff
1159 #define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0
1161 #define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff
1162 #define PINCTRL_IRQEN0_IRQEN_OFFSET 0
1164 #define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff
1165 #define PINCTRL_IRQEN1_IRQEN_OFFSET 0
1167 #define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff
1168 #define PINCTRL_IRQEN2_IRQEN_OFFSET 0
1170 #define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff
1171 #define PINCTRL_IRQEN3_IRQEN_OFFSET 0
1173 #define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff
1174 #define PINCTRL_IRQEN4_IRQEN_OFFSET 0
1176 #define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff
1177 #define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0
1179 #define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff
1180 #define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0
1182 #define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff
1183 #define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0
1185 #define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff
1186 #define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0
1188 #define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff
1189 #define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0
1191 #define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff
1192 #define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0
1194 #define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff
1195 #define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0
1197 #define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff
1198 #define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0
1200 #define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff
1201 #define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0
1203 #define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff
1204 #define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0
1206 #define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff
1207 #define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0
1209 #define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff
1210 #define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0
1212 #define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff
1213 #define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0
1215 #define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff
1216 #define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0
1218 #define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff
1219 #define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0
1221 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26)
1223 #define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24)
1225 #define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22)
1227 #define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20)
1229 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18)
1231 #define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16)
1233 #define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14)
1235 #define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12)
1237 #define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10)
1239 #define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8)
1241 #define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6)
1243 #define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4)
1245 #define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2)
1247 #define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0)
1248 #define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0
1250 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16)
1252 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16)
1253 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16)
1254 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16)
1255 #define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16)
1256 #define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12)
1258 #define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10)
1260 #define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8)
1262 #define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6)
1264 #define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4)
1266 #define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2)
1268 #define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0)
1269 #define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0