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57 #define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
58 #define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
59 #define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
60 #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
61 #define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
62 #define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
84 #define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28)
85 #define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28
86 #define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
87 #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
88 #define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
89 #define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
111 #define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28)
112 #define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28
119 #define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
181 #define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
232 #define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28)
233 #define CLKCTRL_HSADC_FREQDIV_OFFSET 28
237 #define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28)