Lines Matching +full:0 +full:xb0000
12 #define ROM_SW_INFO_ADDR 0x000001E8
13 #define ROMCP_ARB_BASE_ADDR 0x00000000
14 #define ROMCP_ARB_END_ADDR 0x00017FFF
16 #define CAAM_ARB_BASE_ADDR 0x00100000
17 #define CAAM_ARB_END_ADDR 0x00107FFF
18 #define GIC400_ARB_BASE_ADDR 0x31000000
19 #define GIC400_ARB_END_ADDR 0x31007FFF
20 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
21 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
22 #define M4_BOOTROM_BASE_ADDR 0x00180000
25 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
26 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
29 #define GPV0_BASE_ADDR 0x32000000
30 #define GPV1_BASE_ADDR 0x32100000
31 #define GPV2_BASE_ADDR 0x32200000
32 #define GPV3_BASE_ADDR 0x32300000
33 #define GPV4_BASE_ADDR 0x32400000
34 #define GPV5_BASE_ADDR 0x32500000
35 #define GPV6_BASE_ADDR 0x32600000
36 #define GPV7_BASE_ADDR 0x32700000
38 #define OCRAM_ARB_BASE_ADDR 0x00900000
39 #define OCRAM_ARB_END_ADDR 0x0091FFFF
40 #define OCRAM_EPDC_BASE_ADDR 0x00920000
41 #define OCRAM_EPDC_END_ADDR 0x0093FFFF
42 #define OCRAM_PXP_BASE_ADDR 0x00940000
43 #define OCRAM_PXP_END_ADDR 0x00947FFF
45 #define IRAM_SIZE 0x00020000
47 #define AIPS1_ARB_BASE_ADDR 0x30000000
48 #define AIPS1_ARB_END_ADDR 0x303FFFFF
49 #define AIPS2_ARB_BASE_ADDR 0x30400000
50 #define AIPS2_ARB_END_ADDR 0x307FFFFF
51 #define AIPS3_ARB_BASE_ADDR 0x30800000
52 #define AIPS3_ARB_END_ADDR 0x30BFFFFF
54 #define WEIM_ARB_BASE_ADDR 0x28000000
55 #define WEIM_ARB_END_ADDR 0x2FFFFFFF
57 #define QSPI0_ARB_BASE_ADDR 0x60000000
58 #define QSPI0_ARB_END_ADDR 0x6FFFFFFF
59 #define PCIE_ARB_BASE_ADDR 0x40000000
60 #define PCIE_ARB_END_ADDR 0x4FFFFFFF
61 #define PCIE_REG_BASE_ADDR 0x33800000
62 #define PCIE_REG_END_ADDR 0x33803FFF
64 #define MMDC0_ARB_BASE_ADDR 0x80000000
65 #define MMDC0_ARB_END_ADDR 0xBFFFFFFF
66 #define MMDC1_ARB_BASE_ADDR 0xC0000000
67 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
70 #define ARM_PERIPHBASE 0x31000000
72 #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
73 #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
85 #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
87 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
90 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
91 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
92 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
93 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
94 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
95 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
96 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
97 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
98 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
99 #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
100 #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
101 #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
102 #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
104 #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
105 #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
106 #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
107 #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
108 #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
109 #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
111 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
112 #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
113 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
114 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
115 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
116 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
117 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
118 #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
119 #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
120 #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
121 #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
124 #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
126 #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
127 #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
128 #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
129 #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
130 #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
131 #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
132 #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
133 #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
134 #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
135 #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
136 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
137 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
138 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
139 #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
140 #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
142 #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
143 #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
144 #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
145 #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
146 #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
147 #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
148 #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
149 #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
150 #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
151 #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
152 #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
153 #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
155 /* AIPS_TZ#3 - Global enable (0) */
156 #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
157 #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
158 #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
159 #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
160 #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
161 #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
162 #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
163 #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
164 #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
165 #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
166 #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
169 #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
171 #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
173 #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
174 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
175 #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
176 #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
177 #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
178 #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
179 #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
180 #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
181 #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
182 #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
183 #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
184 #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
185 #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
186 #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
187 #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
188 #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
189 #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
190 #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
191 #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
192 #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
193 #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
194 #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
195 #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
196 #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
197 #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
198 #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
199 #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
200 #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
218 #define SNVS_LPGPR 0x68
219 #define CONFIG_SYS_FSL_SEC_OFFSET 0
222 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
267 #define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET 0
268 #define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0)
273 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
274 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
275 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
277 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
279 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
281 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
283 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
285 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
290 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
291 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
292 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
295 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
297 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
300 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
302 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
305 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
307 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
310 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
312 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
314 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
316 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
318 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
320 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
322 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
324 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
326 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
328 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
331 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
334 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
335 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
336 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
338 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
340 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
342 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
344 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
346 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
348 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
350 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
352 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
354 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
356 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
358 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
360 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
362 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
364 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
366 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
369 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
371 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
373 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
375 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
377 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
379 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
381 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
383 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
386 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
387 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
388 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
390 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
392 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
394 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
396 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
398 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
400 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
402 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
404 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
406 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
408 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
410 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
412 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
414 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
416 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
418 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
420 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
422 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
424 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
426 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
428 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
430 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
432 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
434 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
436 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
438 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
440 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
442 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
444 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
446 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
448 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
451 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
452 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
453 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
455 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
457 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
459 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
461 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
463 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
465 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
467 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
469 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
471 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
473 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
475 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
477 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
479 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
481 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
483 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
486 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
490 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
492 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
494 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
496 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
498 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
500 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
502 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
504 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
506 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
508 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
510 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
512 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
514 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
516 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
518 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
520 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
522 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
525 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
526 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
527 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
529 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
531 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
534 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
535 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
536 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
538 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
540 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
542 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
545 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
547 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
549 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
551 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
553 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
556 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
558 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
561 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
564 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
567 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
568 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
569 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
573 #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
574 #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
575 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
577 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
579 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
581 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
585 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
586 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
587 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
590 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
592 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
595 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
597 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
601 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
602 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
603 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
605 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
607 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
609 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
611 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
614 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
617 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
621 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
622 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
623 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
625 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
627 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
629 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
631 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
633 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
635 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
637 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
639 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
641 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
643 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
645 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
647 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
649 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
651 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
653 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
656 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
659 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
661 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
663 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
665 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
668 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
669 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
670 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
673 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
674 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
675 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
677 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
680 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
684 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
685 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
687 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
689 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
691 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
693 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
695 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
698 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
700 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
702 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
704 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
707 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
709 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
711 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
714 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
716 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
718 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
721 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
722 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
724 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
728 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
729 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
731 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
734 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
737 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
740 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
742 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
745 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
748 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
750 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
752 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
754 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
757 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
758 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
759 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
762 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
764 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
767 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
768 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
770 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
773 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
776 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
778 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
780 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
784 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
785 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
787 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
790 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
793 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
796 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
799 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
802 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
804 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
807 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
810 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
812 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
814 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
816 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
818 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
820 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
822 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
825 #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
826 #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
827 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
835 u32 gpr[23]; /* 0x000 */
854 #define MXC_CSPICTRL_EN (1 << 0)
857 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
858 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
859 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
860 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
861 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
862 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
863 #define MXC_CSPICTRL_MAXBITS 0xfff
873 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
884 #define CSU_INIT_SEC_LEVEL0 0x00FF00FF
923 u32 rsvd13[0xc3];
925 struct fuse_bank { /* offset 0x400 */
926 u32 fuse_regs[0x10];
997 u32 rsvd[0xe];
1058 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
1065 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
1067 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
1069 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
1071 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
1075 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
1077 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
1086 #define LCDIF_CTRL_RUN (1 << 0)
1096 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
1108 #define LCDIF_CTRL1_RESET (1 << 0)
1110 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
1112 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
1113 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
1114 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
1115 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
1116 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
1118 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
1120 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
1121 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
1122 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
1123 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
1124 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
1125 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
1126 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
1128 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
1129 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
1130 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
1131 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
1132 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
1133 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
1137 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
1139 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
1142 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
1144 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
1145 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
1147 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
1148 #define LCDIF_CUR_BUF_ADDR_OFFSET 0
1150 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
1151 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0
1153 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
1155 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
1157 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
1159 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
1160 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0
1172 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
1173 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
1175 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
1176 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
1178 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
1180 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
1181 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
1185 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
1187 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
1188 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
1190 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
1193 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
1194 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
1205 #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
1206 readl(USBOTG2_IPS_BASE_ADDR + 0x158))
1207 #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
1210 #define BOOT_TYPE_SD 0x1
1211 #define BOOT_TYPE_MMC 0x2
1212 #define BOOT_TYPE_NAND 0x3
1213 #define BOOT_TYPE_QSPI 0x4
1214 #define BOOT_TYPE_WEIM 0x5
1215 #define BOOT_TYPE_SPINOR 0x6