Lines Matching +full:0 +full:x021b0000
125 #define MX6SL_IOM_DDR_BASE 0x020e0300
151 #define MX6SL_IOM_GRP_BASE 0x020e0500
168 #define MX6UL_IOM_DDR_BASE 0x020e0200
191 #define MX6UL_IOM_GRP_BASE 0x020e0400
206 #define MX6SX_IOM_DDR_BASE 0x020e0200
232 #define MX6SX_IOM_GRP_BASE 0x020e0500
252 #define MX6DQ_IOM_DDR_BASE 0x020e0500
287 #define MX6DQ_IOM_GRP_BASE 0x020e0700
310 #define MX6SDL_IOM_DDR_BASE 0x020e0400
343 #define MX6SDL_IOM_GRP_BASE 0x020e0700
377 u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
397 u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
400 char cs1_mirror;/* enable address mirror (0|1) */
404 u8 ralat; /* Read Additional Latency (0-7) */
405 u8 walat; /* Write Additional Latency (0-3) */
410 u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
475 #define MX6_MMDC_P0_MDCTL 0x021b0000
476 #define MX6_MMDC_P0_MDPDC 0x021b0004
477 #define MX6_MMDC_P0_MDOTC 0x021b0008
478 #define MX6_MMDC_P0_MDCFG0 0x021b000c
479 #define MX6_MMDC_P0_MDCFG1 0x021b0010
480 #define MX6_MMDC_P0_MDCFG2 0x021b0014
481 #define MX6_MMDC_P0_MDMISC 0x021b0018
482 #define MX6_MMDC_P0_MDSCR 0x021b001c
483 #define MX6_MMDC_P0_MDREF 0x021b0020
484 #define MX6_MMDC_P0_MDRWD 0x021b002c
485 #define MX6_MMDC_P0_MDOR 0x021b0030
486 #define MX6_MMDC_P0_MDASP 0x021b0040
487 #define MX6_MMDC_P0_MAPSR 0x021b0404
488 #define MX6_MMDC_P0_MPZQHWCTRL 0x021b0800
489 #define MX6_MMDC_P0_MPWLDECTRL0 0x021b080c
490 #define MX6_MMDC_P0_MPWLDECTRL1 0x021b0810
491 #define MX6_MMDC_P0_MPODTCTRL 0x021b0818
492 #define MX6_MMDC_P0_MPRDDQBY0DL 0x021b081c
493 #define MX6_MMDC_P0_MPRDDQBY1DL 0x021b0820
494 #define MX6_MMDC_P0_MPRDDQBY2DL 0x021b0824
495 #define MX6_MMDC_P0_MPRDDQBY3DL 0x021b0828
496 #define MX6_MMDC_P0_MPDGCTRL0 0x021b083c
497 #define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
498 #define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
499 #define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
500 #define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
501 #define MX6_MMDC_P0_MPMUR0 0x021b08b8
503 #define MX6_MMDC_P1_MDCTL 0x021b4000
504 #define MX6_MMDC_P1_MDPDC 0x021b4004
505 #define MX6_MMDC_P1_MDOTC 0x021b4008
506 #define MX6_MMDC_P1_MDCFG0 0x021b400c
507 #define MX6_MMDC_P1_MDCFG1 0x021b4010
508 #define MX6_MMDC_P1_MDCFG2 0x021b4014
509 #define MX6_MMDC_P1_MDMISC 0x021b4018
510 #define MX6_MMDC_P1_MDSCR 0x021b401c
511 #define MX6_MMDC_P1_MDREF 0x021b4020
512 #define MX6_MMDC_P1_MDRWD 0x021b402c
513 #define MX6_MMDC_P1_MDOR 0x021b4030
514 #define MX6_MMDC_P1_MDASP 0x021b4040
515 #define MX6_MMDC_P1_MAPSR 0x021b4404
516 #define MX6_MMDC_P1_MPZQHWCTRL 0x021b4800
517 #define MX6_MMDC_P1_MPWLDECTRL0 0x021b480c
518 #define MX6_MMDC_P1_MPWLDECTRL1 0x021b4810
519 #define MX6_MMDC_P1_MPODTCTRL 0x021b4818
520 #define MX6_MMDC_P1_MPRDDQBY0DL 0x021b481c
521 #define MX6_MMDC_P1_MPRDDQBY1DL 0x021b4820
522 #define MX6_MMDC_P1_MPRDDQBY2DL 0x021b4824
523 #define MX6_MMDC_P1_MPRDDQBY3DL 0x021b4828
524 #define MX6_MMDC_P1_MPDGCTRL0 0x021b483c
525 #define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
526 #define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
527 #define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
528 #define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
529 #define MX6_MMDC_P1_MPMUR0 0x021b48b8