Lines Matching +full:0 +full:xf7030000

13 #define HI6220_MMC0_BASE			0xF723D000
14 #define HI6220_MMC1_BASE			0xF723E000
16 #define HI6220_UART0_BASE			0xF8015000
17 #define HI6220_UART3_BASE			0xF7113000
19 #define HI6220_PMUSSI_BASE			0xF8000000
21 #define HI6220_PERI_BASE			0xF7030000
24 	u32 ctrl1;		/*0x0*/
39 	u32 ddr_ctrl0;		/*0x50*/
43 	u32 stat1;		/*0x94*/
47 	u32 clk0_en;		/*0x200*/
53 	u32 clk1_en;		/*0x210*/
59 	u32 clk2_en;		/*0x220*/
65 	u32 clk3_en;		/*0x230*/
71 	u32 clk8_en;		/*0x240*/
77 	u32 clk9_en;		/*0x250*/
83 	u32 clk10_en;		/*0x260*/
89 	u32 clk12_en;		/*0x270*/
95 	u32 rst0_en;		/*0x300*/
101 	u32 rst1_en;		/*0x310*/
107 	u32 rst2_en;		/*0x320*/
113 	u32 rst3_en;		/*0x330*/
119 	u32 rst8_en;		/*0x340*/
125 	u32 clk0_sel;		/*0x400*/
129 	u32 clkcfg8bit1;	/*0x494*/
134 	u32 reserved8_addr;	/*0xd04*/
140 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N			(1 << 0)
150 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0		(1 << 0)
167 #define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR		(1 << 0)
179 #define PERI_CTRL4_PICO_FSELV				(1 << 0)
221 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA		(1 << 0)
230 #define PERI_CTRL8_PICOPHY_TXRISETUNE0			(1 << 0)
243 #define PERI_CTRL9_PICOPLY_TESTCLKEN			(1 << 0)
250 #define PERI_CLK0_MMC0					(1 << 0)
260 #define PERI_CLK1_HIFI					(1 << 0)
265 #define PERI_CLK2_IPF					(1 << 0)
276 #define PERI_CLK8_RS0					(1 << 0)
297 #define PERI_CLK9_CARM_DAP				(1 << 0)
304 #define PERI_CLK10_IPF_CCPU				(1 << 0)
315 #define PERI_CLK12_HIFI_SRC				(1 << 0)
329 #define PERI_RST0_MMC0					(1 << 0)
340 #define PERI_RST1_HIFI					(1 << 0)
345 #define PERI_RST2_IPF					(1 << 0)
357 #define PERI_RST3_CSSYS					(1 << 0)
376 #define PERI_RST8_RS0					(1 << 0)