Lines Matching +full:0 +full:x900000
25 #define EP93XX_AHB_BASE 0x80000000
26 #define EP93XX_APB_BASE 0x80800000
29 * 0x80000000 - 0x8000FFFF: DMA
31 #define DMA_OFFSET 0x000000
74 * 0x80010000 - 0x8001FFFF: Ethernet MAC
76 #define MAC_OFFSET 0x010000
156 #define SELFCTL_RESET (1 << 0)
187 #define BMCTL_RXEN (1 << 0)
192 #define BMSTS_QID_MASK 0x07
193 #define BMSTS_QID_RXDATA 0x00
194 #define BMSTS_QID_TXDATA 0x01
195 #define BMSTS_QID_RXSTS 0x02
196 #define BMSTS_QID_TXSTS 0x03
197 #define BMSTS_QID_RXDESC 0x04
198 #define BMSTS_QID_TXDESC 0x05
200 #define AFP_MASK 0x07
201 #define AFP_IAPRIMARY 0x00
202 #define AFP_IASECONDARY1 0x01
203 #define AFP_IASECONDARY2 0x02
204 #define AFP_IASECONDARY3 0x03
205 #define AFP_TX 0x06
206 #define AFP_HASH 0x07
222 #define RXCTL_IA0 (1 << 0)
231 #define TXCTL_STXON (1 << 0)
233 #define MIICMD_REGAD_MASK (0x001F)
234 #define MIICMD_PHYAD_MASK (0x03E0)
235 #define MIICMD_OPCODE_MASK (0xC000)
236 #define MIICMD_PHYAD_8950 (0x0000)
237 #define MIICMD_OPCODE_READ (0x8000)
238 #define MIICMD_OPCODE_WRITE (0x4000)
240 #define MIISTS_BUSY (1 << 0)
243 * 0x80020000 - 0x8002FFFF: USB OHCI
245 #define USB_OFFSET 0x020000
249 * 0x80030000 - 0x8003FFFF: Raster engine
252 #define RASTER_OFFSET 0x030000
257 * 0x80040000 - 0x8004FFFF: Graphics accelerator
260 #define GFX_OFFSET 0x040000
265 * 0x80050000 - 0x8005FFFF: Reserved
269 * 0x80060000 - 0x8006FFFF: SDRAM controller
271 #define SDRAM_OFFSET 0x060000
290 #define SDRAM_DEVCFG_CASLAT_2 0x00010000
291 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
293 #define SDRAM_OFF_GLCONFIG 0x0004
294 #define SDRAM_OFF_REFRSHTIMR 0x0008
296 #define SDRAM_OFF_DEVCFG0 0x0010
297 #define SDRAM_OFF_DEVCFG1 0x0014
298 #define SDRAM_OFF_DEVCFG2 0x0018
299 #define SDRAM_OFF_DEVCFG3 0x001C
301 #define SDRAM_DEVCFG0_BASE 0xC0000000
302 #define SDRAM_DEVCFG1_BASE 0xD0000000
303 #define SDRAM_DEVCFG2_BASE 0xE0000000
304 #define SDRAM_DEVCFG3_ASD0_BASE 0xF0000000
305 #define SDRAM_DEVCFG3_ASD1_BASE 0x00000000
307 #define GLCONFIG_INIT (1 << 0)
315 #define EP93XX_SDRAMCTRL 0x80060000
316 #define EP93XX_SDRAMCTRL_GLOBALCFG_INIT 0x00000001
317 #define EP93XX_SDRAMCTRL_GLOBALCFG_MRS 0x00000002
318 #define EP93XX_SDRAMCTRL_GLOBALCFG_SMEMBUSY 0x00000020
319 #define EP93XX_SDRAMCTRL_GLOBALCFG_LCR 0x00000040
320 #define EP93XX_SDRAMCTRL_GLOBALCFG_REARBEN 0x00000080
321 #define EP93XX_SDRAMCTRL_GLOBALCFG_CLKSHUTDOWN 0x40000000
322 #define EP93XX_SDRAMCTRL_GLOBALCFG_CKE 0x80000000
324 #define EP93XX_SDRAMCTRL_REFRESH_MASK 0x0000FFFF
326 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_32 0x00000002
327 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_16 0x00000001
328 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_8 0x00000000
329 #define EP93XX_SDRAMCTRL_BOOTSTATUS_WIDTH_MASK 0x00000003
330 #define EP93XX_SDRAMCTRL_BOOTSTATUS_MEDIA 0x00000004
332 #define EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH 0x00000004
333 #define EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT 0x00000008
334 #define EP93XX_SDRAMCTRL_DEVCFG_SROM512 0x00000010
335 #define EP93XX_SDRAMCTRL_DEVCFG_SROMLL 0x00000020
336 #define EP93XX_SDRAMCTRL_DEVCFG_2KPAGE 0x00000040
337 #define EP93XX_SDRAMCTRL_DEVCFG_SFCONFIGADDR 0x00000080
338 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_MASK 0x00070000
339 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 0x00010000
340 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_3 0x00020000
341 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_4 0x00030000
342 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_5 0x00040000
343 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_6 0x00050000
344 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_7 0x00060000
345 #define EP93XX_SDRAMCTRL_DEVCFG_CASLAT_8 0x00070000
346 #define EP93XX_SDRAMCTRL_DEVCFG_WBL 0x00080000
347 #define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_MASK 0x00300000
348 #define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 0x00200000
349 #define EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_3 0x00300000
350 #define EP93XX_SDRAMCTRL_DEVCFG_AUTOPRECHARGE 0x01000000
353 * 0x80070000 - 0x8007FFFF: Reserved
357 * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
359 #define SMC_OFFSET 0x080000
381 #define EP93XX_OFF_SMCBCR0 0x00
382 #define EP93XX_OFF_SMCBCR1 0x04
383 #define EP93XX_OFF_SMCBCR2 0x08
384 #define EP93XX_OFF_SMCBCR3 0x0C
385 #define EP93XX_OFF_SMCBCR6 0x18
386 #define EP93XX_OFF_SMCBCR7 0x1C
388 #define SMC_BCR_IDCY_SHIFT 0
395 * 0x80090000 - 0x8009FFFF: Boot ROM
399 * 0x800A0000 - 0x800AFFFF: IDE interface
403 * 0x800B0000 - 0x800BFFFF: VIC1
407 * 0x800C0000 - 0x800CFFFF: VIC2
411 * 0x800D0000 - 0x800FFFFF: Reserved
415 * 0x80800000 - 0x8080FFFF: Reserved
419 * 0x80810000 - 0x8081FFFF: Timers
421 #define TIMER_OFFSET 0x010000
449 * 0x80820000 - 0x8082FFFF: I2S
451 #define I2S_OFFSET 0x020000
455 * 0x80830000 - 0x8083FFFF: Security
457 #define SECURITY_OFFSET 0x030000
460 #define EXTENSIONID (SECURITY_BASE + 0x2714)
463 * 0x80840000 - 0x8084FFFF: GPIO
465 #define GPIO_OFFSET 0x040000
509 #define EP93XX_LED_DATA 0x80840020
510 #define EP93XX_LED_GREEN_ON 0x0001
511 #define EP93XX_LED_RED_ON 0x0002
513 #define EP93XX_LED_DDR 0x80840024
514 #define EP93XX_LED_GREEN_ENABLE 0x0001
515 #define EP93XX_LED_RED_ENABLE 0x00020000
518 * 0x80850000 - 0x8087FFFF: Reserved
522 * 0x80880000 - 0x8088FFFF: AAC
524 #define AAC_OFFSET 0x080000
528 * 0x80890000 - 0x8089FFFF: Reserved
532 * 0x808A0000 - 0x808AFFFF: SPI
534 #define SPI_OFFSET 0x0A0000
538 * 0x808B0000 - 0x808BFFFF: IrDA
540 #define IRDA_OFFSET 0x0B0000
544 * 0x808C0000 - 0x808CFFFF: UART1
546 #define UART1_OFFSET 0x0C0000
550 * 0x808D0000 - 0x808DFFFF: UART2
552 #define UART2_OFFSET 0x0D0000
556 * 0x808E0000 - 0x808EFFFF: UART3
558 #define UART3_OFFSET 0x0E0000
562 * 0x808F0000 - 0x808FFFFF: Key Matrix
564 #define KEY_OFFSET 0x0F0000
568 * 0x80900000 - 0x8090FFFF: Touchscreen
570 #define TOUCH_OFFSET 0x900000
574 * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
576 #define PWM_OFFSET 0x910000
580 * 0x80920000 - 0x8092FFFF: Real time clock
582 #define RTC_OFFSET 0x920000
586 * 0x80930000 - 0x8093FFFF: Syscon
588 #define SYSCON_OFFSET 0x930000
592 #define SECURITY_EXTENSIONID 0x80832714
625 #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
628 #define SYSCON_OFF_CLKSET1 0x0020
629 #define SYSCON_OFF_SYSCFG 0x009c
634 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
647 #define SYSCON_CHIPID_REV_MASK 0xF0000000
650 #define SYSCON_SYSCFG_LASDO 0x00000020
653 * 0x80930000 - 0x8093FFFF: Watchdog Timer
655 #define WATCHDOG_OFFSET 0x940000
659 * 0x80950000 - 0x9000FFFF: Reserved
665 #define UBOOT_MEMORYCNF_BANK_SIZE 0x2000
666 #define UBOOT_MEMORYCNF_BANK_MASK 0x2004
667 #define UBOOT_MEMORYCNF_BANK_COUNT 0x2008