Lines Matching +full:0 +full:xd4014000

16 #define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
20 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
23 #define FE_CLK_RST		0x1
24 #define FE_CLK_ENA		0x8
27 #define SSP2_APBCLK		0x01
28 #define SSP2_FNCLK		0x02
31 #define USB_SPH_AXICLK_EN	0x10
32 #define USB_SPH_AXI_RST		0x02
39 #define ARMD1_DRAM_BASE		0xB0000000
40 #define ARMD1_FEC_BASE		0xC0800000
41 #define ARMD1_TIMER_BASE	0xD4014000
42 #define ARMD1_APBC1_BASE	0xD4015000
43 #define ARMD1_APBC2_BASE	0xD4015800
44 #define ARMD1_UART1_BASE	0xD4017000
45 #define ARMD1_UART2_BASE	0xD4018000
46 #define ARMD1_GPIO_BASE		0xD4019000
47 #define ARMD1_SSP1_BASE		0xD401B000
48 #define ARMD1_SSP2_BASE		0xD401C000
49 #define ARMD1_MFPR_BASE		0xD401E000
50 #define ARMD1_SSP3_BASE		0xD401F000
51 #define ARMD1_SSP4_BASE		0xD4020000
52 #define ARMD1_SSP5_BASE		0xD4021000
53 #define ARMD1_UART3_BASE	0xD4026000
54 #define ARMD1_MPMU_BASE		0xD4050000
55 #define ARMD1_USB_HOST_BASE	0xD4209000
56 #define ARMD1_APMU_BASE		0xD4282800
57 #define ARMD1_CPU_BASE		0xD4282C00