Lines Matching +full:0 +full:xf01
18 #size-cells = <0>;
20 cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
55 CPU_SLEEP_0: cpu-sleep-0 {
57 arm,psci-suspend-param = <0x40000000>;
76 #power-domain-cells = <0x0>;
77 pd-id = <0x16>;
81 #power-domain-cells = <0x0>;
82 pd-id = <0x17>;
86 #power-domain-cells = <0x0>;
87 pd-id = <0x1c>;
91 #power-domain-cells = <0x0>;
92 pd-id = <0x23>;
96 #power-domain-cells = <0x0>;
97 pd-id = <0x24>;
101 #power-domain-cells = <0x0>;
102 pd-id = <0x21>;
106 #power-domain-cells = <0x0>;
107 pd-id = <0x22>;
111 #power-domain-cells = <0x0>;
112 pd-id = <0x1d>;
116 #power-domain-cells = <0x0>;
117 pd-id = <0x1e>;
121 #power-domain-cells = <0x0>;
122 pd-id = <0x1f>;
126 #power-domain-cells = <0x0>;
127 pd-id = <0x20>;
131 #power-domain-cells = <0x0>;
132 pd-id = <0x25>;
136 #power-domain-cells = <0x0>;
137 pd-id = <0x26>;
142 #power-domain-cells = <0x0>;
143 pd-id = <0x29>;
147 #power-domain-cells = <0x0>;
148 pd-id = <0x2a>;
152 #power-domain-cells = <0x0>;
153 pd-id = <0x2b>;
157 #power-domain-cells = <0x0>;
158 pd-id = <0x18>;
162 #power-domain-cells = <0x0>;
163 pd-id = <0x19>;
167 #power-domain-cells = <0x0>;
168 pd-id = <0x1a>;
172 #power-domain-cells = <0x0>;
173 pd-id = <0x1b>;
177 #power-domain-cells = <0x0>;
178 pd-id = <0x27>;
182 #power-domain-cells = <0x0>;
183 pd-id = <0x28>;
187 #power-domain-cells = <0x0>;
188 pd-id = <0x2c>;
192 #power-domain-cells = <0x0>;
193 pd-id = <0x2d>;
197 #power-domain-cells = <0x0>;
198 pd-id = <0x2e>;
202 #power-domain-cells = <0x0>;
203 pd-id = <0x2f>;
207 #power-domain-cells = <0x0>;
208 pd-id = <0x30>;
212 #power-domain-cells = <0x0>;
213 pd-id = <0x3b>;
217 #power-domain-cells = <0x0>;
218 pd-id = <0x3a 0x14 0x15>;
225 interrupts = <0 143 4>,
226 <0 144 4>,
227 <0 145 4>,
228 <0 146 4>;
244 interrupts = <1 13 0xf01>,
245 <1 14 0xf01>,
246 <1 11 0xf01>,
247 <1 10 0xf01>;
258 amba_apu: amba_apu@0 {
262 ranges = <0 0 0 0 0xffffffff>;
267 reg = <0x0 0xf9010000 0x10000>,
268 <0x0 0xf9020000 0x20000>,
269 <0x0 0xf9040000 0x20000>,
270 <0x0 0xf9060000 0x20000>;
273 interrupts = <1 9 0xf04>;
288 reg = <0x0 0xff060000 0x0 0x1000>;
289 interrupts = <0 23 4>;
291 tx-fifo-depth = <0x40>;
292 rx-fifo-depth = <0x40>;
300 reg = <0x0 0xff070000 0x0 0x1000>;
301 interrupts = <0 24 4>;
303 tx-fifo-depth = <0x40>;
304 rx-fifo-depth = <0x40>;
310 reg = <0x0 0xfd6e0000 0x0 0x9000>;
311 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
317 reg = <0x9000 0x5000>;
319 interrupts = <0 123 4>,
320 <0 123 4>,
321 <0 123 4>,
322 <0 123 4>,
323 <0 123 4>;
331 reg = <0x0 0xfd500000 0x0 0x1000>;
333 interrupts = <0 124 4>;
337 iommus = <&smmu 0x14e8>;
344 reg = <0x0 0xfd510000 0x0 0x1000>;
346 interrupts = <0 125 4>;
350 iommus = <&smmu 0x14e9>;
357 reg = <0x0 0xfd520000 0x0 0x1000>;
359 interrupts = <0 126 4>;
363 iommus = <&smmu 0x14ea>;
370 reg = <0x0 0xfd530000 0x0 0x1000>;
372 interrupts = <0 127 4>;
376 iommus = <&smmu 0x14eb>;
383 reg = <0x0 0xfd540000 0x0 0x1000>;
385 interrupts = <0 128 4>;
389 iommus = <&smmu 0x14ec>;
396 reg = <0x0 0xfd550000 0x0 0x1000>;
398 interrupts = <0 129 4>;
402 iommus = <&smmu 0x14ed>;
409 reg = <0x0 0xfd560000 0x0 0x1000>;
411 interrupts = <0 130 4>;
415 iommus = <&smmu 0x14ee>;
422 reg = <0x0 0xfd570000 0x0 0x1000>;
424 interrupts = <0 131 4>;
428 iommus = <&smmu 0x14ef>;
435 reg = <0x0 0xfd4b0000 0x0 0x30000>;
437 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
450 reg = <0x0 0xffa80000 0x0 0x1000>;
452 interrupts = <0 77 4>;
455 iommus = <&smmu 0x868>;
463 reg = <0x0 0xffa90000 0x0 0x1000>;
465 interrupts = <0 78 4>;
468 iommus = <&smmu 0x869>;
476 reg = <0x0 0xffaa0000 0x0 0x1000>;
478 interrupts = <0 79 4>;
481 iommus = <&smmu 0x86a>;
489 reg = <0x0 0xffab0000 0x0 0x1000>;
491 interrupts = <0 80 4>;
494 iommus = <&smmu 0x86b>;
502 reg = <0x0 0xffac0000 0x0 0x1000>;
504 interrupts = <0 81 4>;
507 iommus = <&smmu 0x86c>;
515 reg = <0x0 0xffad0000 0x0 0x1000>;
517 interrupts = <0 82 4>;
520 iommus = <&smmu 0x86d>;
528 reg = <0x0 0xffae0000 0x0 0x1000>;
530 interrupts = <0 83 4>;
533 iommus = <&smmu 0x86e>;
541 reg = <0x0 0xffaf0000 0x0 0x1000>;
543 interrupts = <0 84 4>;
546 iommus = <&smmu 0x86f>;
552 reg = <0x0 0xfd070000 0x0 0x30000>;
554 interrupts = <0 112 4>;
560 reg = <0x0 0xff100000 0x0 0x1000>;
563 interrupts = <0 14 4>;
567 iommus = <&smmu 0x872>;
575 interrupts = <0 57 4>, <0 57 4>;
576 reg = <0x0 0xff0b0000 0x0 0x1000>;
579 #size-cells = <0>;
581 iommus = <&smmu 0x874>;
589 interrupts = <0 59 4>, <0 59 4>;
590 reg = <0x0 0xff0c0000 0x0 0x1000>;
593 #size-cells = <0>;
595 iommus = <&smmu 0x875>;
603 interrupts = <0 61 4>, <0 61 4>;
604 reg = <0x0 0xff0d0000 0x0 0x1000>;
607 #size-cells = <0>;
609 iommus = <&smmu 0x876>;
617 interrupts = <0 63 4>, <0 63 4>;
618 reg = <0x0 0xff0e0000 0x0 0x1000>;
621 #size-cells = <0>;
623 iommus = <&smmu 0x877>;
630 #gpio-cells = <0x2>;
632 interrupts = <0 16 4>;
635 reg = <0x0 0xff0a0000 0x0 0x1000>;
643 interrupts = <0 17 4>;
644 reg = <0x0 0xff020000 0x0 0x1000>;
646 #size-cells = <0>;
654 interrupts = <0 18 4>;
655 reg = <0x0 0xff030000 0x0 0x1000>;
657 #size-cells = <0>;
663 reg = <0x0 0xff960000 0x0 0x1000>;
665 interrupts = <0 10 4>;
677 interrupts = <0 118 4>,
678 <0 117 4>,
679 <0 116 4>,
680 <0 115 4>, /* MSI_1 [63...32] */
681 <0 114 4>; /* MSI_0 [31...0] */
684 reg = <0x0 0xfd0e0000 0x0 0x1000>,
685 <0x0 0xfd480000 0x0 0x1000>,
686 <0x80 0x00000000 0x0 0x1000000>;
688 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-pref…
689 …0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memo…
690 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
691 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
692 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
693 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
694 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
698 #address-cells = <0>;
707 interrupts = <0 15 4>;
710 reg = <0x0 0xff0f0000 0x0 0x1000>,
711 <0x0 0xc0000000 0x0 0x8000000>;
713 #size-cells = <0>;
715 iommus = <&smmu 0x873>;
722 reg = <0x0 0xffa60000 0x0 0x100>;
724 interrupts = <0 26 4>, <0 27 4>;
731 reg = <0x0 0xfd400000 0x0 0x40000>,
732 <0x0 0xfd3d0000 0x0 0x1000>,
733 <0x0 0xfd1a0000 0x0 0x1000>,
734 <0x0 0xff5e0000 0x0 0x1000>;
754 reg = <0x0 0xfd0c0000 0x0 0x2000>;
756 interrupts = <0 133 4>;
765 interrupts = <0 48 4>;
766 reg = <0x0 0xff160000 0x0 0x1000>;
768 xlnx,device_id = <0>;
770 iommus = <&smmu 0x870>;
779 interrupts = <0 49 4>;
780 reg = <0x0 0xff170000 0x0 0x1000>;
784 iommus = <&smmu 0x871>;
790 reg = <0x0 0xfd800000 0x0 0x20000>;
794 interrupts = <0 155 4>,
795 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
796 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
797 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
798 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
799 mmu-masters = < &gem0 0x874
800 &gem1 0x875
801 &gem2 0x876
802 &gem3 0x877
803 &usb0 0x860
804 &usb1 0x861
805 &qspi 0x873
806 &lpd_dma_chan1 0x868
807 &lpd_dma_chan2 0x869
808 &lpd_dma_chan3 0x86a
809 &lpd_dma_chan4 0x86b
810 &lpd_dma_chan5 0x86c
811 &lpd_dma_chan6 0x86d
812 &lpd_dma_chan7 0x86e
813 &lpd_dma_chan8 0x86f
814 &fpd_dma_chan1 0x14e8
815 &fpd_dma_chan2 0x14e9
816 &fpd_dma_chan3 0x14ea
817 &fpd_dma_chan4 0x14eb
818 &fpd_dma_chan5 0x14ec
819 &fpd_dma_chan6 0x14ed
820 &fpd_dma_chan7 0x14ee
821 &fpd_dma_chan8 0x14ef
822 &sdhci0 0x870
823 &sdhci1 0x871
824 &nand0 0x872>;
831 interrupts = <0 19 4>;
832 reg = <0x0 0xff040000 0x0 0x1000>;
835 #size-cells = <0>;
843 interrupts = <0 20 4>;
844 reg = <0x0 0xff050000 0x0 0x1000>;
847 #size-cells = <0>;
855 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
856 reg = <0x0 0xff110000 0x0 0x1000>;
865 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
866 reg = <0x0 0xff120000 0x0 0x1000>;
875 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
876 reg = <0x0 0xff130000 0x0 0x1000>;
885 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
886 reg = <0x0 0xff140000 0x0 0x1000>;
896 interrupts = <0 21 4>;
897 reg = <0x0 0xff000000 0x0 0x1000>;
907 interrupts = <0 22 4>;
908 reg = <0x0 0xff010000 0x0 0x1000>;
921 iommus = <&smmu 0x860>;
928 reg = <0x0 0xfe200000 0x0 0x40000>;
930 interrupts = <0 65 4>;
931 /* snps,quirk-frame-length-adjustment = <0x20>; */
944 iommus = <&smmu 0x861>;
951 reg = <0x0 0xfe300000 0x0 0x40000>;
953 interrupts = <0 70 4>;
954 /* snps,quirk-frame-length-adjustment = <0x20>; */
963 interrupts = <0 113 1>;
964 reg = <0x0 0xfd4d0000 0x0 0x1000>;
981 dmas = <&xlnx_dpdma 0>,
992 reg = <0x0 0xfd4a0000 0x0 0x1000>;
993 interrupts = <0 119 4>;
1038 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1039 <0x0 0xfd4ab000 0x0 0x1000>,
1040 <0x0 0xfd4ac000 0x0 0x1000>;
1050 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1051 interrupts = <0 122 4>;