arm/dts/zynqmp-clk.dtsi

2  * Clock specification for Xilinx ZynqMP
8  * SPDX-License-Identifier:	GPL-2.0+
13 		compatible = "fixed-clock";
14 		#clock-cells = <0>;
15 		clock-frequency = <100000000>;
16 		u-boot,dm-pre-reloc;
20 		compatible = "fixed-clock";
21 		#clock-cells = <0>;
22 		clock-frequency = <125000000>;
26 		compatible = "fixed-clock";
27 		#clock-cells = <0>;
28 		clock-frequency = <200000000>;
32 		compatible = "fixed-clock";
33 		#clock-cells = <0>;
34 		clock-frequency = <250000000>;
38 		compatible = "fixed-clock";
39 		#clock-cells = <0>;
40 		clock-frequency = <300000000>;
44 		compatible = "fixed-clock";
45 		#clock-cells = <0>;
46 		clock-frequency = <600000000>;
50 		compatible = "fixed-clock";
51 		#clock-cells = <0>;
52 		clock-frequency = <100000000>;
53 		clock-accuracy = <100>;
57 		compatible = "fixed-clock";
58 		#clock-cells = <0>;
59 		clock-frequency = <24576000>;
60 		clock-accuracy = <100>;
64 		compatible = "fixed-clock";
65 		#clock-cells = <0x0>;
66 		clock-frequency = <533000000>;
70 		compatible = "fixed-clock";
71 		#clock-cells = <0x0>;
72 		clock-frequency = <262750000>;
73 		clock-accuracy = <0x64>;