Lines Matching +full:uniphier +full:- +full:sd4hc
2 * Device Tree Source for UniPhier PXs3 SoC
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 compatible = "socionext,uniphier-pxs3";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
41 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
45 operating-points-v2 = <&cluster0_opp>;
50 compatible = "arm,cortex-a53", "arm,armv8";
53 enable-method = "psci";
54 operating-points-v2 = <&cluster0_opp>;
59 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 operating-points-v2 = <&cluster0_opp>;
68 compatible = "arm,cortex-a53", "arm,armv8";
71 enable-method = "psci";
72 operating-points-v2 = <&cluster0_opp>;
77 compatible = "operating-points-v2";
78 opp-shared;
80 opp-250000000 {
81 opp-hz = /bits/ 64 <250000000>;
82 clock-latency-ns = <300>;
84 opp-325000000 {
85 opp-hz = /bits/ 64 <325000000>;
86 clock-latency-ns = <300>;
88 opp-500000000 {
89 opp-hz = /bits/ 64 <500000000>;
90 clock-latency-ns = <300>;
92 opp-650000000 {
93 opp-hz = /bits/ 64 <650000000>;
94 clock-latency-ns = <300>;
96 opp-666667000 {
97 opp-hz = /bits/ 64 <666667000>;
98 clock-latency-ns = <300>;
100 opp-866667000 {
101 opp-hz = /bits/ 64 <866667000>;
102 clock-latency-ns = <300>;
104 opp-1000000000 {
105 opp-hz = /bits/ 64 <1000000000>;
106 clock-latency-ns = <300>;
108 opp-1300000000 {
109 opp-hz = /bits/ 64 <1300000000>;
110 clock-latency-ns = <300>;
115 compatible = "arm,psci-1.0";
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <25000000>;
128 compatible = "arm,armv8-timer";
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
142 compatible = "socionext,uniphier-uart";
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_uart0>;
149 clock-frequency = <58820000>;
153 compatible = "socionext,uniphier-uart";
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_uart1>;
160 clock-frequency = <58820000>;
164 compatible = "socionext,uniphier-uart";
168 pinctrl-names = "default";
169 pinctrl-0 = <&pinctrl_uart2>;
171 clock-frequency = <58820000>;
175 compatible = "socionext,uniphier-uart";
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_uart3>;
182 clock-frequency = <58820000>;
186 compatible = "socionext,uniphier-pxs3-gpio";
188 interrupt-parent = <&aidet>;
189 interrupt-controller;
190 #interrupt-cells = <2>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 gpio-ranges = <&pinctrl 0 0 0>,
196 gpio-ranges-group-names = "gpio_range0",
202 compatible = "socionext,uniphier-fi2c";
205 #address-cells = <1>;
206 #size-cells = <0>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_i2c0>;
211 clock-frequency = <100000>;
215 compatible = "socionext,uniphier-fi2c";
218 #address-cells = <1>;
219 #size-cells = <0>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&pinctrl_i2c1>;
224 clock-frequency = <100000>;
228 compatible = "socionext,uniphier-fi2c";
231 #address-cells = <1>;
232 #size-cells = <0>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_i2c2>;
237 clock-frequency = <100000>;
241 compatible = "socionext,uniphier-fi2c";
244 #address-cells = <1>;
245 #size-cells = <0>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_i2c3>;
250 clock-frequency = <100000>;
253 /* chip-internal connection for HDMI */
255 compatible = "socionext,uniphier-fi2c";
257 #address-cells = <1>;
258 #size-cells = <0>;
261 clock-frequency = <400000>;
264 system_bus: system-bus@58c00000 {
265 compatible = "socionext,uniphier-system-bus";
268 #address-cells = <2>;
269 #size-cells = <1>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_system_bus>;
275 compatible = "socionext,uniphier-smpctrl";
280 compatible = "socionext,uniphier-pxs3-sdctrl",
281 "simple-mfd", "syscon";
285 compatible = "socionext,uniphier-pxs3-sd-clock";
286 #clock-cells = <1>;
290 compatible = "socionext,uniphier-pxs3-sd-reset";
291 #reset-cells = <1>;
296 compatible = "socionext,uniphier-pxs3-perictrl",
297 "simple-mfd", "syscon";
301 compatible = "socionext,uniphier-pxs3-peri-clock";
302 #clock-cells = <1>;
306 compatible = "socionext,uniphier-pxs3-peri-reset";
307 #reset-cells = <1>;
312 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
315 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_emmc_1v8>;
318 bus-width = <8>;
319 mmc-ddr-1_8v;
320 mmc-hs200-1_8v;
321 cdns,phy-input-delay-legacy = <4>;
322 cdns,phy-input-delay-mmc-highspeed = <2>;
323 cdns,phy-input-delay-mmc-ddr = <3>;
324 cdns,phy-dll-delay-sdclk = <21>;
325 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
329 compatible = "socionext,uniphier-sdhc";
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_sd>;
336 reset-names = "host";
338 bus-width = <4>;
339 cap-sd-highspeed;
342 soc-glue@5f800000 {
343 compatible = "socionext,uniphier-pxs3-soc-glue",
344 "simple-mfd", "syscon";
348 compatible = "socionext,uniphier-pxs3-pinctrl";
353 compatible = "socionext,uniphier-pxs3-aidet";
355 interrupt-controller;
356 #interrupt-cells = <2>;
359 gic: interrupt-controller@5fe00000 {
360 compatible = "arm,gic-v3";
363 interrupt-controller;
364 #interrupt-cells = <3>;
369 compatible = "socionext,uniphier-pxs3-sysctrl",
370 "simple-mfd", "syscon";
374 compatible = "socionext,uniphier-pxs3-clock";
375 #clock-cells = <1>;
379 compatible = "socionext,uniphier-pxs3-reset";
380 #reset-cells = <1>;
384 compatible = "socionext,uniphier-wdt";
389 compatible = "socionext,uniphier-pxs3-dwc3";
392 #address-cells = <1>;
393 #size-cells = <1>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
402 tx-fifo-resize;
407 compatible = "socionext,uniphier-pxs3-dwc3";
410 #address-cells = <1>;
411 #size-cells = <1>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
420 tx-fifo-resize;
425 compatible = "socionext,uniphier-denali-nand-v5b";
427 reg-names = "nand_data", "denali_reg";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_nand>;
437 #include "uniphier-pinctrl.dtsi"