Lines Matching +full:uniphier +full:- +full:perictrl
2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pxs2";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "arm,cortex-a9";
44 enable-method = "psci";
45 next-level-cache = <&l2>;
46 operating-points-v2 = <&cpu_opp>;
51 compatible = "arm,cortex-a9";
54 enable-method = "psci";
55 next-level-cache = <&l2>;
56 operating-points-v2 = <&cpu_opp>;
61 compatible = "operating-points-v2";
62 opp-shared;
64 opp-100000000 {
65 opp-hz = /bits/ 64 <100000000>;
66 clock-latency-ns = <300>;
68 opp-150000000 {
69 opp-hz = /bits/ 64 <150000000>;
70 clock-latency-ns = <300>;
72 opp-200000000 {
73 opp-hz = /bits/ 64 <200000000>;
74 clock-latency-ns = <300>;
76 opp-300000000 {
77 opp-hz = /bits/ 64 <300000000>;
78 clock-latency-ns = <300>;
80 opp-400000000 {
81 opp-hz = /bits/ 64 <400000000>;
82 clock-latency-ns = <300>;
84 opp-600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
88 opp-800000000 {
89 opp-hz = /bits/ 64 <800000000>;
90 clock-latency-ns = <300>;
92 opp-1200000000 {
93 opp-hz = /bits/ 64 <1200000000>;
94 clock-latency-ns = <300>;
99 compatible = "arm,psci-0.2";
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <25000000>;
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <50000000>;
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
122 interrupt-parent = <&intc>;
123 u-boot,dm-pre-reloc;
125 l2: l2-cache@500c0000 {
126 compatible = "socionext,uniphier-system-cache";
130 cache-unified;
131 cache-size = <(1280 * 1024)>;
132 cache-sets = <512>;
133 cache-line-size = <128>;
134 cache-level = <2>;
138 compatible = "socionext,uniphier-uart";
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_uart0>;
145 clock-frequency = <88900000>;
149 compatible = "socionext,uniphier-uart";
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart1>;
156 clock-frequency = <88900000>;
160 compatible = "socionext,uniphier-uart";
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart2>;
167 clock-frequency = <88900000>;
171 compatible = "socionext,uniphier-uart";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_uart3>;
178 clock-frequency = <88900000>;
182 compatible = "socionext,uniphier-gpio";
184 gpio-controller;
185 #gpio-cells = <2>;
189 compatible = "socionext,uniphier-gpio";
191 gpio-controller;
192 #gpio-cells = <2>;
196 compatible = "socionext,uniphier-gpio";
198 gpio-controller;
199 #gpio-cells = <2>;
203 compatible = "socionext,uniphier-gpio";
205 gpio-controller;
206 #gpio-cells = <2>;
210 compatible = "socionext,uniphier-gpio";
212 gpio-controller;
213 #gpio-cells = <2>;
217 compatible = "socionext,uniphier-gpio";
219 gpio-controller;
220 #gpio-cells = <2>;
224 compatible = "socionext,uniphier-gpio";
226 gpio-controller;
227 #gpio-cells = <2>;
231 compatible = "socionext,uniphier-gpio";
233 gpio-controller;
234 #gpio-cells = <2>;
238 compatible = "socionext,uniphier-gpio";
240 gpio-controller;
241 #gpio-cells = <2>;
245 compatible = "socionext,uniphier-gpio";
247 gpio-controller;
248 #gpio-cells = <2>;
252 compatible = "socionext,uniphier-gpio";
254 gpio-controller;
255 #gpio-cells = <2>;
259 compatible = "socionext,uniphier-gpio";
261 gpio-controller;
262 #gpio-cells = <2>;
266 compatible = "socionext,uniphier-gpio";
268 gpio-controller;
269 #gpio-cells = <2>;
273 compatible = "socionext,uniphier-gpio";
275 gpio-controller;
276 #gpio-cells = <2>;
280 compatible = "socionext,uniphier-gpio";
282 gpio-controller;
283 #gpio-cells = <2>;
287 compatible = "socionext,uniphier-gpio";
289 gpio-controller;
290 #gpio-cells = <2>;
294 compatible = "socionext,uniphier-gpio";
296 gpio-controller;
297 #gpio-cells = <2>;
301 compatible = "socionext,uniphier-gpio";
303 gpio-controller;
304 #gpio-cells = <2>;
308 compatible = "socionext,uniphier-gpio";
310 gpio-controller;
311 #gpio-cells = <2>;
315 compatible = "socionext,uniphier-gpio";
317 gpio-controller;
318 #gpio-cells = <2>;
322 compatible = "socionext,uniphier-gpio";
324 gpio-controller;
325 #gpio-cells = <2>;
329 compatible = "socionext,uniphier-gpio";
331 gpio-controller;
332 #gpio-cells = <2>;
336 compatible = "socionext,uniphier-gpio";
338 gpio-controller;
339 #gpio-cells = <2>;
343 compatible = "socionext,uniphier-gpio";
345 gpio-controller;
346 #gpio-cells = <2>;
350 compatible = "socionext,uniphier-gpio";
352 gpio-controller;
353 #gpio-cells = <2>;
357 compatible = "socionext,uniphier-gpio";
359 gpio-controller;
360 #gpio-cells = <2>;
364 compatible = "socionext,uniphier-gpio";
366 gpio-controller;
367 #gpio-cells = <2>;
371 compatible = "socionext,uniphier-gpio";
373 gpio-controller;
374 #gpio-cells = <2>;
378 compatible = "socionext,uniphier-fi2c";
381 #address-cells = <1>;
382 #size-cells = <0>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_i2c0>;
387 clock-frequency = <100000>;
391 compatible = "socionext,uniphier-fi2c";
394 #address-cells = <1>;
395 #size-cells = <0>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_i2c1>;
400 clock-frequency = <100000>;
404 compatible = "socionext,uniphier-fi2c";
407 #address-cells = <1>;
408 #size-cells = <0>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_i2c2>;
413 clock-frequency = <100000>;
417 compatible = "socionext,uniphier-fi2c";
420 #address-cells = <1>;
421 #size-cells = <0>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_i2c3>;
426 clock-frequency = <100000>;
429 /* chip-internal connection for DMD */
431 compatible = "socionext,uniphier-fi2c";
433 #address-cells = <1>;
434 #size-cells = <0>;
437 clock-frequency = <400000>;
440 /* chip-internal connection for STM */
442 compatible = "socionext,uniphier-fi2c";
444 #address-cells = <1>;
445 #size-cells = <0>;
448 clock-frequency = <400000>;
451 /* chip-internal connection for HDMI */
453 compatible = "socionext,uniphier-fi2c";
455 #address-cells = <1>;
456 #size-cells = <0>;
459 clock-frequency = <400000>;
462 system_bus: system-bus@58c00000 {
463 compatible = "socionext,uniphier-system-bus";
466 #address-cells = <2>;
467 #size-cells = <1>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_system_bus>;
473 compatible = "socionext,uniphier-smpctrl";
478 compatible = "socionext,uniphier-pxs2-sdctrl",
479 "simple-mfd", "syscon";
481 u-boot,dm-pre-reloc;
484 compatible = "socionext,uniphier-pxs2-sd-clock";
485 #clock-cells = <1>;
489 compatible = "socionext,uniphier-pxs2-sd-reset";
490 #reset-cells = <1>;
494 perictrl@59820000 {
495 compatible = "socionext,uniphier-pxs2-perictrl",
496 "simple-mfd", "syscon";
500 compatible = "socionext,uniphier-pxs2-peri-clock";
501 #clock-cells = <1>;
505 compatible = "socionext,uniphier-pxs2-peri-reset";
506 #reset-cells = <1>;
511 compatible = "socionext,uniphier-sdhc";
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_emmc>;
518 reset-names = "host";
520 bus-width = <8>;
521 non-removable;
522 cap-mmc-highspeed;
523 cap-mmc-hw-reset;
524 no-3-3-v;
528 compatible = "socionext,uniphier-sdhc";
532 pinctrl-names = "default", "1.8v";
533 pinctrl-0 = <&pinctrl_sd>;
534 pinctrl-1 = <&pinctrl_sd_1v8>;
536 reset-names = "host";
538 bus-width = <4>;
539 cap-sd-highspeed;
540 sd-uhs-sdr12;
541 sd-uhs-sdr25;
542 sd-uhs-sdr50;
545 soc-glue@5f800000 {
546 compatible = "socionext,uniphier-pxs2-soc-glue",
547 "simple-mfd", "syscon";
549 u-boot,dm-pre-reloc;
552 compatible = "socionext,uniphier-pxs2-pinctrl";
553 u-boot,dm-pre-reloc;
558 compatible = "socionext,uniphier-pxs2-aidet";
560 interrupt-controller;
561 #interrupt-cells = <2>;
565 compatible = "arm,cortex-a9-global-timer";
572 compatible = "arm,cortex-a9-twd-timer";
578 intc: interrupt-controller@60001000 {
579 compatible = "arm,cortex-a9-gic";
582 #interrupt-cells = <3>;
583 interrupt-controller;
587 compatible = "socionext,uniphier-pxs2-sysctrl",
588 "simple-mfd", "syscon";
592 compatible = "socionext,uniphier-pxs2-clock";
593 #clock-cells = <1>;
597 compatible = "socionext,uniphier-pxs2-reset";
598 #reset-cells = <1>;
603 compatible = "socionext,uniphier-pxs2-dwc3";
606 #address-cells = <1>;
607 #size-cells = <1>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
616 tx-fifo-resize;
621 compatible = "socionext,uniphier-pxs2-dwc3";
624 #address-cells = <1>;
625 #size-cells = <1>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
634 tx-fifo-resize;
639 compatible = "socionext,uniphier-denali-nand-v5b";
641 reg-names = "nand_data", "denali_reg";
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_nand2cs>;
651 #include "uniphier-pinctrl.dtsi"