Lines Matching +full:cache +full:- +full:controller +full:- +full:0
4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pxs2";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu@0 {
21 compatible = "arm,cortex-a9";
22 reg = <0>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "arm,cortex-a9";
44 enable-method = "psci";
45 next-level-cache = <&l2>;
46 operating-points-v2 = <&cpu_opp>;
51 compatible = "arm,cortex-a9";
54 enable-method = "psci";
55 next-level-cache = <&l2>;
56 operating-points-v2 = <&cpu_opp>;
61 compatible = "operating-points-v2";
62 opp-shared;
64 opp-100000000 {
65 opp-hz = /bits/ 64 <100000000>;
66 clock-latency-ns = <300>;
68 opp-150000000 {
69 opp-hz = /bits/ 64 <150000000>;
70 clock-latency-ns = <300>;
72 opp-200000000 {
73 opp-hz = /bits/ 64 <200000000>;
74 clock-latency-ns = <300>;
76 opp-300000000 {
77 opp-hz = /bits/ 64 <300000000>;
78 clock-latency-ns = <300>;
80 opp-400000000 {
81 opp-hz = /bits/ 64 <400000000>;
82 clock-latency-ns = <300>;
84 opp-600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
88 opp-800000000 {
89 opp-hz = /bits/ 64 <800000000>;
90 clock-latency-ns = <300>;
92 opp-1200000000 {
93 opp-hz = /bits/ 64 <1200000000>;
94 clock-latency-ns = <300>;
99 compatible = "arm,psci-0.2";
105 compatible = "fixed-clock";
106 #clock-cells = <0>;
107 clock-frequency = <25000000>;
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-frequency = <50000000>;
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
122 interrupt-parent = <&intc>;
123 u-boot,dm-pre-reloc;
125 l2: l2-cache@500c0000 {
126 compatible = "socionext,uniphier-system-cache";
127 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
128 <0x506c0000 0x400>;
129 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
130 cache-unified;
131 cache-size = <(1280 * 1024)>;
132 cache-sets = <512>;
133 cache-line-size = <128>;
134 cache-level = <2>;
138 compatible = "socionext,uniphier-uart";
140 reg = <0x54006800 0x40>;
141 interrupts = <0 33 4>;
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_uart0>;
144 clocks = <&peri_clk 0>;
145 clock-frequency = <88900000>;
149 compatible = "socionext,uniphier-uart";
151 reg = <0x54006900 0x40>;
152 interrupts = <0 35 4>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_uart1>;
156 clock-frequency = <88900000>;
160 compatible = "socionext,uniphier-uart";
162 reg = <0x54006a00 0x40>;
163 interrupts = <0 37 4>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart2>;
167 clock-frequency = <88900000>;
171 compatible = "socionext,uniphier-uart";
173 reg = <0x54006b00 0x40>;
174 interrupts = <0 177 4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_uart3>;
178 clock-frequency = <88900000>;
182 compatible = "socionext,uniphier-gpio";
183 reg = <0x55000008 0x8>;
184 gpio-controller;
185 #gpio-cells = <2>;
189 compatible = "socionext,uniphier-gpio";
190 reg = <0x55000010 0x8>;
191 gpio-controller;
192 #gpio-cells = <2>;
196 compatible = "socionext,uniphier-gpio";
197 reg = <0x55000018 0x8>;
198 gpio-controller;
199 #gpio-cells = <2>;
203 compatible = "socionext,uniphier-gpio";
204 reg = <0x55000020 0x8>;
205 gpio-controller;
206 #gpio-cells = <2>;
210 compatible = "socionext,uniphier-gpio";
211 reg = <0x55000028 0x8>;
212 gpio-controller;
213 #gpio-cells = <2>;
217 compatible = "socionext,uniphier-gpio";
218 reg = <0x55000030 0x8>;
219 gpio-controller;
220 #gpio-cells = <2>;
224 compatible = "socionext,uniphier-gpio";
225 reg = <0x55000038 0x8>;
226 gpio-controller;
227 #gpio-cells = <2>;
231 compatible = "socionext,uniphier-gpio";
232 reg = <0x55000040 0x8>;
233 gpio-controller;
234 #gpio-cells = <2>;
238 compatible = "socionext,uniphier-gpio";
239 reg = <0x55000048 0x8>;
240 gpio-controller;
241 #gpio-cells = <2>;
245 compatible = "socionext,uniphier-gpio";
246 reg = <0x55000050 0x8>;
247 gpio-controller;
248 #gpio-cells = <2>;
252 compatible = "socionext,uniphier-gpio";
253 reg = <0x55000058 0x8>;
254 gpio-controller;
255 #gpio-cells = <2>;
259 compatible = "socionext,uniphier-gpio";
260 reg = <0x55000068 0x8>;
261 gpio-controller;
262 #gpio-cells = <2>;
266 compatible = "socionext,uniphier-gpio";
267 reg = <0x55000070 0x8>;
268 gpio-controller;
269 #gpio-cells = <2>;
273 compatible = "socionext,uniphier-gpio";
274 reg = <0x55000078 0x8>;
275 gpio-controller;
276 #gpio-cells = <2>;
280 compatible = "socionext,uniphier-gpio";
281 reg = <0x55000080 0x8>;
282 gpio-controller;
283 #gpio-cells = <2>;
287 compatible = "socionext,uniphier-gpio";
288 reg = <0x55000088 0x8>;
289 gpio-controller;
290 #gpio-cells = <2>;
294 compatible = "socionext,uniphier-gpio";
295 reg = <0x550000a0 0x8>;
296 gpio-controller;
297 #gpio-cells = <2>;
301 compatible = "socionext,uniphier-gpio";
302 reg = <0x550000a8 0x8>;
303 gpio-controller;
304 #gpio-cells = <2>;
308 compatible = "socionext,uniphier-gpio";
309 reg = <0x550000b0 0x8>;
310 gpio-controller;
311 #gpio-cells = <2>;
315 compatible = "socionext,uniphier-gpio";
316 reg = <0x550000b8 0x8>;
317 gpio-controller;
318 #gpio-cells = <2>;
322 compatible = "socionext,uniphier-gpio";
323 reg = <0x550000c0 0x8>;
324 gpio-controller;
325 #gpio-cells = <2>;
329 compatible = "socionext,uniphier-gpio";
330 reg = <0x550000c8 0x8>;
331 gpio-controller;
332 #gpio-cells = <2>;
336 compatible = "socionext,uniphier-gpio";
337 reg = <0x550000d0 0x8>;
338 gpio-controller;
339 #gpio-cells = <2>;
343 compatible = "socionext,uniphier-gpio";
344 reg = <0x550000d8 0x8>;
345 gpio-controller;
346 #gpio-cells = <2>;
350 compatible = "socionext,uniphier-gpio";
351 reg = <0x550000e0 0x8>;
352 gpio-controller;
353 #gpio-cells = <2>;
357 compatible = "socionext,uniphier-gpio";
358 reg = <0x550000e8 0x8>;
359 gpio-controller;
360 #gpio-cells = <2>;
364 compatible = "socionext,uniphier-gpio";
365 reg = <0x550000f0 0x8>;
366 gpio-controller;
367 #gpio-cells = <2>;
371 compatible = "socionext,uniphier-gpio";
372 reg = <0x550000f8 0x8>;
373 gpio-controller;
374 #gpio-cells = <2>;
378 compatible = "socionext,uniphier-fi2c";
380 reg = <0x58780000 0x80>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383 interrupts = <0 41 4>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_i2c0>;
387 clock-frequency = <100000>;
391 compatible = "socionext,uniphier-fi2c";
393 reg = <0x58781000 0x80>;
394 #address-cells = <1>;
395 #size-cells = <0>;
396 interrupts = <0 42 4>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_i2c1>;
400 clock-frequency = <100000>;
404 compatible = "socionext,uniphier-fi2c";
406 reg = <0x58782000 0x80>;
407 #address-cells = <1>;
408 #size-cells = <0>;
409 interrupts = <0 43 4>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_i2c2>;
413 clock-frequency = <100000>;
417 compatible = "socionext,uniphier-fi2c";
419 reg = <0x58783000 0x80>;
420 #address-cells = <1>;
421 #size-cells = <0>;
422 interrupts = <0 44 4>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&pinctrl_i2c3>;
426 clock-frequency = <100000>;
429 /* chip-internal connection for DMD */
431 compatible = "socionext,uniphier-fi2c";
432 reg = <0x58784000 0x80>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 interrupts = <0 45 4>;
437 clock-frequency = <400000>;
440 /* chip-internal connection for STM */
442 compatible = "socionext,uniphier-fi2c";
443 reg = <0x58785000 0x80>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 interrupts = <0 25 4>;
448 clock-frequency = <400000>;
451 /* chip-internal connection for HDMI */
453 compatible = "socionext,uniphier-fi2c";
454 reg = <0x58786000 0x80>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 interrupts = <0 26 4>;
459 clock-frequency = <400000>;
462 system_bus: system-bus@58c00000 {
463 compatible = "socionext,uniphier-system-bus";
465 reg = <0x58c00000 0x400>;
466 #address-cells = <2>;
467 #size-cells = <1>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pinctrl_system_bus>;
473 compatible = "socionext,uniphier-smpctrl";
474 reg = <0x59801000 0x400>;
478 compatible = "socionext,uniphier-pxs2-sdctrl",
479 "simple-mfd", "syscon";
480 reg = <0x59810000 0x400>;
481 u-boot,dm-pre-reloc;
484 compatible = "socionext,uniphier-pxs2-sd-clock";
485 #clock-cells = <1>;
489 compatible = "socionext,uniphier-pxs2-sd-reset";
490 #reset-cells = <1>;
495 compatible = "socionext,uniphier-pxs2-perictrl",
496 "simple-mfd", "syscon";
497 reg = <0x59820000 0x200>;
500 compatible = "socionext,uniphier-pxs2-peri-clock";
501 #clock-cells = <1>;
505 compatible = "socionext,uniphier-pxs2-peri-reset";
506 #reset-cells = <1>;
511 compatible = "socionext,uniphier-sdhc";
513 reg = <0x5a000000 0x800>;
514 interrupts = <0 78 4>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_emmc>;
518 reset-names = "host";
520 bus-width = <8>;
521 non-removable;
522 cap-mmc-highspeed;
523 cap-mmc-hw-reset;
524 no-3-3-v;
528 compatible = "socionext,uniphier-sdhc";
530 reg = <0x5a400000 0x800>;
531 interrupts = <0 76 4>;
532 pinctrl-names = "default", "1.8v";
533 pinctrl-0 = <&pinctrl_sd>;
534 pinctrl-1 = <&pinctrl_sd_1v8>;
535 clocks = <&sd_clk 0>;
536 reset-names = "host";
537 resets = <&sd_rst 0>;
538 bus-width = <4>;
539 cap-sd-highspeed;
540 sd-uhs-sdr12;
541 sd-uhs-sdr25;
542 sd-uhs-sdr50;
545 soc-glue@5f800000 {
546 compatible = "socionext,uniphier-pxs2-soc-glue",
547 "simple-mfd", "syscon";
548 reg = <0x5f800000 0x2000>;
549 u-boot,dm-pre-reloc;
552 compatible = "socionext,uniphier-pxs2-pinctrl";
553 u-boot,dm-pre-reloc;
558 compatible = "socionext,uniphier-pxs2-aidet";
559 reg = <0x5fc20000 0x200>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
565 compatible = "arm,cortex-a9-global-timer";
566 reg = <0x60000200 0x20>;
567 interrupts = <1 11 0xf04>;
572 compatible = "arm,cortex-a9-twd-timer";
573 reg = <0x60000600 0x20>;
574 interrupts = <1 13 0xf04>;
578 intc: interrupt-controller@60001000 {
579 compatible = "arm,cortex-a9-gic";
580 reg = <0x60001000 0x1000>,
581 <0x60000100 0x100>;
582 #interrupt-cells = <3>;
583 interrupt-controller;
587 compatible = "socionext,uniphier-pxs2-sysctrl",
588 "simple-mfd", "syscon";
589 reg = <0x61840000 0x10000>;
592 compatible = "socionext,uniphier-pxs2-clock";
593 #clock-cells = <1>;
597 compatible = "socionext,uniphier-pxs2-reset";
598 #reset-cells = <1>;
603 compatible = "socionext,uniphier-pxs2-dwc3";
605 reg = <0x65b00000 0x1000>;
606 #address-cells = <1>;
607 #size-cells = <1>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
613 reg = <0x65a00000 0x10000>;
614 interrupts = <0 134 4>;
616 tx-fifo-resize;
621 compatible = "socionext,uniphier-pxs2-dwc3";
623 reg = <0x65d00000 0x1000>;
624 #address-cells = <1>;
625 #size-cells = <1>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
631 reg = <0x65c00000 0x10000>;
632 interrupts = <0 137 4>;
634 tx-fifo-resize;
639 compatible = "socionext,uniphier-denali-nand-v5b";
641 reg-names = "nand_data", "denali_reg";
642 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
643 interrupts = <0 65 4>;
644 pinctrl-names = "default";
645 pinctrl-0 = <&pinctrl_nand2cs>;
651 #include "uniphier-pinctrl.dtsi"