Lines Matching +full:cache +full:- +full:controller +full:- +full:0
4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro5";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu@0 {
21 compatible = "arm,cortex-a9";
22 reg = <0>;
24 enable-method = "psci";
25 next-level-cache = <&l2>;
26 operating-points-v2 = <&cpu_opp>;
31 compatible = "arm,cortex-a9";
34 enable-method = "psci";
35 next-level-cache = <&l2>;
36 operating-points-v2 = <&cpu_opp>;
41 compatible = "operating-points-v2";
42 opp-shared;
44 opp-100000000 {
45 opp-hz = /bits/ 64 <100000000>;
46 clock-latency-ns = <300>;
48 opp-116667000 {
49 opp-hz = /bits/ 64 <116667000>;
50 clock-latency-ns = <300>;
52 opp-150000000 {
53 opp-hz = /bits/ 64 <150000000>;
54 clock-latency-ns = <300>;
56 opp-175000000 {
57 opp-hz = /bits/ 64 <175000000>;
58 clock-latency-ns = <300>;
60 opp-200000000 {
61 opp-hz = /bits/ 64 <200000000>;
62 clock-latency-ns = <300>;
64 opp-233334000 {
65 opp-hz = /bits/ 64 <233334000>;
66 clock-latency-ns = <300>;
68 opp-300000000 {
69 opp-hz = /bits/ 64 <300000000>;
70 clock-latency-ns = <300>;
72 opp-350000000 {
73 opp-hz = /bits/ 64 <350000000>;
74 clock-latency-ns = <300>;
76 opp-400000000 {
77 opp-hz = /bits/ 64 <400000000>;
78 clock-latency-ns = <300>;
80 opp-466667000 {
81 opp-hz = /bits/ 64 <466667000>;
82 clock-latency-ns = <300>;
84 opp-600000000 {
85 opp-hz = /bits/ 64 <600000000>;
86 clock-latency-ns = <300>;
88 opp-700000000 {
89 opp-hz = /bits/ 64 <700000000>;
90 clock-latency-ns = <300>;
92 opp-800000000 {
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
96 opp-933334000 {
97 opp-hz = /bits/ 64 <933334000>;
98 clock-latency-ns = <300>;
100 opp-1200000000 {
101 opp-hz = /bits/ 64 <1200000000>;
102 clock-latency-ns = <300>;
104 opp-1400000000 {
105 opp-hz = /bits/ 64 <1400000000>;
106 clock-latency-ns = <300>;
111 compatible = "arm,psci-0.2";
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-frequency = <20000000>;
123 #clock-cells = <0>;
124 compatible = "fixed-clock";
125 clock-frequency = <50000000>;
130 compatible = "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
134 interrupt-parent = <&intc>;
135 u-boot,dm-pre-reloc;
137 l2: l2-cache@500c0000 {
138 compatible = "socionext,uniphier-system-cache";
139 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
140 <0x506c0000 0x400>;
141 interrupts = <0 190 4>, <0 191 4>;
142 cache-unified;
143 cache-size = <(2 * 1024 * 1024)>;
144 cache-sets = <512>;
145 cache-line-size = <128>;
146 cache-level = <2>;
147 next-level-cache = <&l3>;
150 l3: l3-cache@500c8000 {
151 compatible = "socionext,uniphier-system-cache";
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
154 interrupts = <0 174 4>, <0 175 4>;
155 cache-unified;
156 cache-size = <(2 * 1024 * 1024)>;
157 cache-sets = <512>;
158 cache-line-size = <256>;
159 cache-level = <3>;
163 compatible = "socionext,uniphier-uart";
165 reg = <0x54006800 0x40>;
166 interrupts = <0 33 4>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_uart0>;
169 clocks = <&peri_clk 0>;
170 clock-frequency = <73728000>;
174 compatible = "socionext,uniphier-uart";
176 reg = <0x54006900 0x40>;
177 interrupts = <0 35 4>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_uart1>;
181 clock-frequency = <73728000>;
185 compatible = "socionext,uniphier-uart";
187 reg = <0x54006a00 0x40>;
188 interrupts = <0 37 4>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_uart2>;
192 clock-frequency = <73728000>;
196 compatible = "socionext,uniphier-uart";
198 reg = <0x54006b00 0x40>;
199 interrupts = <0 177 4>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_uart3>;
203 clock-frequency = <73728000>;
207 compatible = "socionext,uniphier-gpio";
208 reg = <0x55000008 0x8>;
209 gpio-controller;
210 #gpio-cells = <2>;
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x55000010 0x8>;
216 gpio-controller;
217 #gpio-cells = <2>;
221 compatible = "socionext,uniphier-gpio";
222 reg = <0x55000018 0x8>;
223 gpio-controller;
224 #gpio-cells = <2>;
228 compatible = "socionext,uniphier-gpio";
229 reg = <0x55000020 0x8>;
230 gpio-controller;
231 #gpio-cells = <2>;
235 compatible = "socionext,uniphier-gpio";
236 reg = <0x55000028 0x8>;
237 gpio-controller;
238 #gpio-cells = <2>;
242 compatible = "socionext,uniphier-gpio";
243 reg = <0x55000030 0x8>;
244 gpio-controller;
245 #gpio-cells = <2>;
249 compatible = "socionext,uniphier-gpio";
250 reg = <0x55000038 0x8>;
251 gpio-controller;
252 #gpio-cells = <2>;
256 compatible = "socionext,uniphier-gpio";
257 reg = <0x55000040 0x8>;
258 gpio-controller;
259 #gpio-cells = <2>;
263 compatible = "socionext,uniphier-gpio";
264 reg = <0x55000048 0x8>;
265 gpio-controller;
266 #gpio-cells = <2>;
270 compatible = "socionext,uniphier-gpio";
271 reg = <0x55000050 0x8>;
272 gpio-controller;
273 #gpio-cells = <2>;
277 compatible = "socionext,uniphier-gpio";
278 reg = <0x55000058 0x8>;
279 gpio-controller;
280 #gpio-cells = <2>;
284 compatible = "socionext,uniphier-gpio";
285 reg = <0x55000060 0x8>;
286 gpio-controller;
287 #gpio-cells = <2>;
291 compatible = "socionext,uniphier-gpio";
292 reg = <0x55000068 0x8>;
293 gpio-controller;
294 #gpio-cells = <2>;
298 compatible = "socionext,uniphier-gpio";
299 reg = <0x55000070 0x8>;
300 gpio-controller;
301 #gpio-cells = <2>;
305 compatible = "socionext,uniphier-gpio";
306 reg = <0x55000078 0x8>;
307 gpio-controller;
308 #gpio-cells = <2>;
312 compatible = "socionext,uniphier-gpio";
313 reg = <0x550000a0 0x8>;
314 gpio-controller;
315 #gpio-cells = <2>;
319 compatible = "socionext,uniphier-gpio";
320 reg = <0x550000a8 0x8>;
321 gpio-controller;
322 #gpio-cells = <2>;
326 compatible = "socionext,uniphier-gpio";
327 reg = <0x550000b0 0x8>;
328 gpio-controller;
329 #gpio-cells = <2>;
333 compatible = "socionext,uniphier-gpio";
334 reg = <0x550000b8 0x8>;
335 gpio-controller;
336 #gpio-cells = <2>;
340 compatible = "socionext,uniphier-gpio";
341 reg = <0x550000c0 0x8>;
342 gpio-controller;
343 #gpio-cells = <2>;
347 compatible = "socionext,uniphier-gpio";
348 reg = <0x550000c8 0x8>;
349 gpio-controller;
350 #gpio-cells = <2>;
354 compatible = "socionext,uniphier-gpio";
355 reg = <0x550000d0 0x8>;
356 gpio-controller;
357 #gpio-cells = <2>;
361 compatible = "socionext,uniphier-gpio";
362 reg = <0x550000d8 0x8>;
363 gpio-controller;
364 #gpio-cells = <2>;
368 compatible = "socionext,uniphier-gpio";
369 reg = <0x550000e0 0x8>;
370 gpio-controller;
371 #gpio-cells = <2>;
375 compatible = "socionext,uniphier-gpio";
376 reg = <0x550000e8 0x8>;
377 gpio-controller;
378 #gpio-cells = <2>;
382 compatible = "socionext,uniphier-gpio";
383 reg = <0x550000f0 0x8>;
384 gpio-controller;
385 #gpio-cells = <2>;
389 compatible = "socionext,uniphier-gpio";
390 reg = <0x550000f8 0x8>;
391 gpio-controller;
392 #gpio-cells = <2>;
396 compatible = "socionext,uniphier-gpio";
397 reg = <0x55000100 0x8>;
398 gpio-controller;
399 #gpio-cells = <2>;
403 compatible = "socionext,uniphier-gpio";
404 reg = <0x55000108 0x8>;
405 gpio-controller;
406 #gpio-cells = <2>;
410 compatible = "socionext,uniphier-fi2c";
412 reg = <0x58780000 0x80>;
413 #address-cells = <1>;
414 #size-cells = <0>;
415 interrupts = <0 41 4>;
416 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_i2c0>;
419 clock-frequency = <100000>;
423 compatible = "socionext,uniphier-fi2c";
425 reg = <0x58781000 0x80>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428 interrupts = <0 42 4>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pinctrl_i2c1>;
432 clock-frequency = <100000>;
436 compatible = "socionext,uniphier-fi2c";
438 reg = <0x58782000 0x80>;
439 #address-cells = <1>;
440 #size-cells = <0>;
441 interrupts = <0 43 4>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_i2c2>;
445 clock-frequency = <100000>;
449 compatible = "socionext,uniphier-fi2c";
451 reg = <0x58783000 0x80>;
452 #address-cells = <1>;
453 #size-cells = <0>;
454 interrupts = <0 44 4>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_i2c3>;
458 clock-frequency = <100000>;
463 /* chip-internal connection for DMD */
465 compatible = "socionext,uniphier-fi2c";
466 reg = <0x58785000 0x80>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 interrupts = <0 25 4>;
471 clock-frequency = <400000>;
474 /* chip-internal connection for HDMI */
476 compatible = "socionext,uniphier-fi2c";
477 reg = <0x58786000 0x80>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 interrupts = <0 26 4>;
482 clock-frequency = <400000>;
485 system_bus: system-bus@58c00000 {
486 compatible = "socionext,uniphier-system-bus";
488 reg = <0x58c00000 0x400>;
489 #address-cells = <2>;
490 #size-cells = <1>;
491 pinctrl-names = "default";
492 pinctrl-0 = <&pinctrl_system_bus>;
496 compatible = "socionext,uniphier-smpctrl";
497 reg = <0x59801000 0x400>;
501 compatible = "socionext,uniphier-pro5-sdctrl",
502 "simple-mfd", "syscon";
503 reg = <0x59810000 0x400>;
504 u-boot,dm-pre-reloc;
507 compatible = "socionext,uniphier-pro5-sd-clock";
508 #clock-cells = <1>;
512 compatible = "socionext,uniphier-pro5-sd-reset";
513 #reset-cells = <1>;
518 compatible = "socionext,uniphier-pro5-perictrl",
519 "simple-mfd", "syscon";
520 reg = <0x59820000 0x200>;
523 compatible = "socionext,uniphier-pro5-peri-clock";
524 #clock-cells = <1>;
528 compatible = "socionext,uniphier-pro5-peri-reset";
529 #reset-cells = <1>;
533 soc-glue@5f800000 {
534 compatible = "socionext,uniphier-pro5-soc-glue",
535 "simple-mfd", "syscon";
536 reg = <0x5f800000 0x2000>;
537 u-boot,dm-pre-reloc;
540 compatible = "socionext,uniphier-pro5-pinctrl";
541 u-boot,dm-pre-reloc;
546 compatible = "socionext,uniphier-pro5-aidet";
547 reg = <0x5fc20000 0x200>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
553 compatible = "arm,cortex-a9-global-timer";
554 reg = <0x60000200 0x20>;
555 interrupts = <1 11 0x304>;
560 compatible = "arm,cortex-a9-twd-timer";
561 reg = <0x60000600 0x20>;
562 interrupts = <1 13 0x304>;
566 intc: interrupt-controller@60001000 {
567 compatible = "arm,cortex-a9-gic";
568 reg = <0x60001000 0x1000>,
569 <0x60000100 0x100>;
570 #interrupt-cells = <3>;
571 interrupt-controller;
575 compatible = "socionext,uniphier-pro5-sysctrl",
576 "simple-mfd", "syscon";
577 reg = <0x61840000 0x10000>;
580 compatible = "socionext,uniphier-pro5-clock";
581 #clock-cells = <1>;
585 compatible = "socionext,uniphier-pro5-reset";
586 #reset-cells = <1>;
591 compatible = "socionext,uniphier-pro5-dwc3";
593 reg = <0x65b00000 0x1000>;
594 #address-cells = <1>;
595 #size-cells = <1>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_usb0>;
601 reg = <0x65a00000 0x10000>;
602 interrupts = <0 134 4>;
604 tx-fifo-resize;
609 compatible = "socionext,uniphier-pro5-dwc3";
611 reg = <0x65d00000 0x1000>;
612 #address-cells = <1>;
613 #size-cells = <1>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>;
619 reg = <0x65c00000 0x10000>;
620 interrupts = <0 137 4>;
622 tx-fifo-resize;
627 compatible = "socionext,uniphier-denali-nand-v5b";
629 reg-names = "nand_data", "denali_reg";
630 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
631 interrupts = <0 65 4>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&pinctrl_nand2cs>;
638 compatible = "socionext,uniphier-sdhc";
640 reg = <0x68400000 0x800>;
641 interrupts = <0 78 4>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&pinctrl_emmc>;
645 reset-names = "host";
647 bus-width = <8>;
648 non-removable;
649 cap-mmc-highspeed;
650 cap-mmc-hw-reset;
651 no-3-3-v;
655 compatible = "socionext,uniphier-sdhc";
657 reg = <0x68800000 0x800>;
658 interrupts = <0 76 4>;
659 pinctrl-names = "default", "1.8v";
660 pinctrl-0 = <&pinctrl_sd>;
661 pinctrl-1 = <&pinctrl_sd_1v8>;
662 clocks = <&sd_clk 0>;
663 reset-names = "host";
664 resets = <&sd_rst 0>;
665 bus-width = <4>;
666 cap-sd-highspeed;
667 sd-uhs-sdr12;
668 sd-uhs-sdr25;
669 sd-uhs-sdr50;
674 #include "uniphier-pinctrl.dtsi"