Lines Matching +full:uniphier +full:- +full:gpio
2 * Device Tree Source for UniPhier Pro4 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 compatible = "arm,cortex-a9";
23 enable-method = "psci";
24 next-level-cache = <&l2>;
29 compatible = "arm,cortex-a9";
31 enable-method = "psci";
32 next-level-cache = <&l2>;
37 compatible = "arm,psci-0.2";
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
60 interrupt-parent = <&intc>;
61 u-boot,dm-pre-reloc;
63 l2: l2-cache@500c0000 {
64 compatible = "socionext,uniphier-system-cache";
68 cache-unified;
69 cache-size = <(768 * 1024)>;
70 cache-sets = <256>;
71 cache-line-size = <128>;
72 cache-level = <2>;
76 compatible = "socionext,uniphier-uart";
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_uart0>;
83 clock-frequency = <73728000>;
87 compatible = "socionext,uniphier-uart";
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_uart1>;
94 clock-frequency = <73728000>;
98 compatible = "socionext,uniphier-uart";
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart2>;
105 clock-frequency = <73728000>;
109 compatible = "socionext,uniphier-uart";
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_uart3>;
116 clock-frequency = <73728000>;
119 port0x: gpio@55000008 {
120 compatible = "socionext,uniphier-gpio";
122 gpio-controller;
123 #gpio-cells = <2>;
126 port1x: gpio@55000010 {
127 compatible = "socionext,uniphier-gpio";
129 gpio-controller;
130 #gpio-cells = <2>;
133 port2x: gpio@55000018 {
134 compatible = "socionext,uniphier-gpio";
136 gpio-controller;
137 #gpio-cells = <2>;
140 port3x: gpio@55000020 {
141 compatible = "socionext,uniphier-gpio";
143 gpio-controller;
144 #gpio-cells = <2>;
147 port4: gpio@55000028 {
148 compatible = "socionext,uniphier-gpio";
150 gpio-controller;
151 #gpio-cells = <2>;
154 port5x: gpio@55000030 {
155 compatible = "socionext,uniphier-gpio";
157 gpio-controller;
158 #gpio-cells = <2>;
161 port6x: gpio@55000038 {
162 compatible = "socionext,uniphier-gpio";
164 gpio-controller;
165 #gpio-cells = <2>;
168 port7x: gpio@55000040 {
169 compatible = "socionext,uniphier-gpio";
171 gpio-controller;
172 #gpio-cells = <2>;
175 port8x: gpio@55000048 {
176 compatible = "socionext,uniphier-gpio";
178 gpio-controller;
179 #gpio-cells = <2>;
182 port9x: gpio@55000050 {
183 compatible = "socionext,uniphier-gpio";
185 gpio-controller;
186 #gpio-cells = <2>;
189 port10x: gpio@55000058 {
190 compatible = "socionext,uniphier-gpio";
192 gpio-controller;
193 #gpio-cells = <2>;
196 port11x: gpio@55000060 {
197 compatible = "socionext,uniphier-gpio";
199 gpio-controller;
200 #gpio-cells = <2>;
203 port12x: gpio@55000068 {
204 compatible = "socionext,uniphier-gpio";
206 gpio-controller;
207 #gpio-cells = <2>;
210 port13x: gpio@55000070 {
211 compatible = "socionext,uniphier-gpio";
213 gpio-controller;
214 #gpio-cells = <2>;
217 port14x: gpio@55000078 {
218 compatible = "socionext,uniphier-gpio";
220 gpio-controller;
221 #gpio-cells = <2>;
224 port17x: gpio@550000a0 {
225 compatible = "socionext,uniphier-gpio";
227 gpio-controller;
228 #gpio-cells = <2>;
231 port18x: gpio@550000a8 {
232 compatible = "socionext,uniphier-gpio";
234 gpio-controller;
235 #gpio-cells = <2>;
238 port19x: gpio@550000b0 {
239 compatible = "socionext,uniphier-gpio";
241 gpio-controller;
242 #gpio-cells = <2>;
245 port20x: gpio@550000b8 {
246 compatible = "socionext,uniphier-gpio";
248 gpio-controller;
249 #gpio-cells = <2>;
252 port21x: gpio@550000c0 {
253 compatible = "socionext,uniphier-gpio";
255 gpio-controller;
256 #gpio-cells = <2>;
259 port22x: gpio@550000c8 {
260 compatible = "socionext,uniphier-gpio";
262 gpio-controller;
263 #gpio-cells = <2>;
266 port23x: gpio@550000d0 {
267 compatible = "socionext,uniphier-gpio";
269 gpio-controller;
270 #gpio-cells = <2>;
273 port24x: gpio@550000d8 {
274 compatible = "socionext,uniphier-gpio";
276 gpio-controller;
277 #gpio-cells = <2>;
280 port25x: gpio@550000e0 {
281 compatible = "socionext,uniphier-gpio";
283 gpio-controller;
284 #gpio-cells = <2>;
287 port26x: gpio@550000e8 {
288 compatible = "socionext,uniphier-gpio";
290 gpio-controller;
291 #gpio-cells = <2>;
294 port27x: gpio@550000f0 {
295 compatible = "socionext,uniphier-gpio";
297 gpio-controller;
298 #gpio-cells = <2>;
301 port28x: gpio@550000f8 {
302 compatible = "socionext,uniphier-gpio";
304 gpio-controller;
305 #gpio-cells = <2>;
308 port29x: gpio@55000100 {
309 compatible = "socionext,uniphier-gpio";
311 gpio-controller;
312 #gpio-cells = <2>;
315 port30x: gpio@55000108 {
316 compatible = "socionext,uniphier-gpio";
318 gpio-controller;
319 #gpio-cells = <2>;
323 compatible = "socionext,uniphier-fi2c";
326 #address-cells = <1>;
327 #size-cells = <0>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c0>;
332 clock-frequency = <100000>;
336 compatible = "socionext,uniphier-fi2c";
339 #address-cells = <1>;
340 #size-cells = <0>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_i2c1>;
345 clock-frequency = <100000>;
349 compatible = "socionext,uniphier-fi2c";
352 #address-cells = <1>;
353 #size-cells = <0>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c2>;
358 clock-frequency = <100000>;
362 compatible = "socionext,uniphier-fi2c";
365 #address-cells = <1>;
366 #size-cells = <0>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_i2c3>;
371 clock-frequency = <100000>;
376 /* chip-internal connection for DMD */
378 compatible = "socionext,uniphier-fi2c";
380 #address-cells = <1>;
381 #size-cells = <0>;
384 clock-frequency = <400000>;
387 /* chip-internal connection for HDMI */
389 compatible = "socionext,uniphier-fi2c";
391 #address-cells = <1>;
392 #size-cells = <0>;
395 clock-frequency = <400000>;
398 system_bus: system-bus@58c00000 {
399 compatible = "socionext,uniphier-system-bus";
402 #address-cells = <2>;
403 #size-cells = <1>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&pinctrl_system_bus>;
409 compatible = "socionext,uniphier-smpctrl";
414 compatible = "socionext,uniphier-pro4-mioctrl",
415 "simple-mfd", "syscon";
417 u-boot,dm-pre-reloc;
420 compatible = "socionext,uniphier-pro4-mio-clock";
421 #clock-cells = <1>;
425 compatible = "socionext,uniphier-pro4-mio-reset";
426 #reset-cells = <1>;
431 compatible = "socionext,uniphier-pro4-perictrl",
432 "simple-mfd", "syscon";
436 compatible = "socionext,uniphier-pro4-peri-clock";
437 #clock-cells = <1>;
441 compatible = "socionext,uniphier-pro4-peri-reset";
442 #reset-cells = <1>;
447 compatible = "socionext,uniphier-sdhc";
451 pinctrl-names = "default", "1.8v";
452 pinctrl-0 = <&pinctrl_sd>;
453 pinctrl-1 = <&pinctrl_sd_1v8>;
455 reset-names = "host", "bridge";
457 bus-width = <4>;
458 cap-sd-highspeed;
459 sd-uhs-sdr12;
460 sd-uhs-sdr25;
461 sd-uhs-sdr50;
465 compatible = "socionext,uniphier-sdhc";
469 pinctrl-names = "default", "1.8v";
470 pinctrl-0 = <&pinctrl_emmc>;
471 pinctrl-1 = <&pinctrl_emmc_1v8>;
473 reset-names = "host", "bridge";
475 bus-width = <8>;
476 non-removable;
477 cap-mmc-highspeed;
478 cap-mmc-hw-reset;
482 compatible = "socionext,uniphier-sdhc";
486 pinctrl-names = "default", "1.8v";
487 pinctrl-0 = <&pinctrl_sd1>;
488 pinctrl-1 = <&pinctrl_sd1_1v8>;
491 bus-width = <4>;
492 cap-sd-highspeed;
493 sd-uhs-sdr12;
494 sd-uhs-sdr25;
495 sd-uhs-sdr50;
499 compatible = "socionext,uniphier-ehci", "generic-ehci";
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_usb2>;
511 compatible = "socionext,uniphier-ehci", "generic-ehci";
515 pinctrl-names = "default";
516 pinctrl-0 = <&pinctrl_usb3>;
522 soc-glue@5f800000 {
523 compatible = "socionext,uniphier-pro4-soc-glue",
524 "simple-mfd", "syscon";
526 u-boot,dm-pre-reloc;
529 compatible = "socionext,uniphier-pro4-pinctrl";
530 u-boot,dm-pre-reloc;
535 compatible = "socionext,uniphier-pro4-aidet";
537 interrupt-controller;
538 #interrupt-cells = <2>;
542 compatible = "arm,cortex-a9-global-timer";
549 compatible = "arm,cortex-a9-twd-timer";
555 intc: interrupt-controller@60001000 {
556 compatible = "arm,cortex-a9-gic";
559 #interrupt-cells = <3>;
560 interrupt-controller;
564 compatible = "socionext,uniphier-pro4-sysctrl",
565 "simple-mfd", "syscon";
569 compatible = "socionext,uniphier-pro4-clock";
570 #clock-cells = <1>;
574 compatible = "socionext,uniphier-pro4-reset";
575 #reset-cells = <1>;
580 compatible = "socionext,uniphier-pro4-dwc3";
583 #address-cells = <1>;
584 #size-cells = <1>;
586 pinctrl-names = "default";
587 pinctrl-0 = <&pinctrl_usb0>;
593 tx-fifo-resize;
598 compatible = "socionext,uniphier-pro4-dwc3";
601 #address-cells = <1>;
602 #size-cells = <1>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_usb1>;
611 tx-fifo-resize;
616 compatible = "socionext,uniphier-denali-nand-v5a";
618 reg-names = "nand_data", "denali_reg";
621 pinctrl-names = "default";
622 pinctrl-0 = <&pinctrl_nand>;
628 #include "uniphier-pinctrl.dtsi"