arm/dts/uniphier-ld20.dtsi

2  * Device Tree Source for UniPhier LD20 SoC
4  * Copyright (C) 2015-2016 Socionext Inc.
7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 	compatible = "socionext,uniphier-ld20";
14 	#address-cells = <2>;
15 	#size-cells = <2>;
16 	interrupt-parent = <&gic>;
19 		#address-cells = <2>;
20 		#size-cells = <0>;
22 		cpu-map {
44 			compatible = "arm,cortex-a72", "arm,armv8";
47 			enable-method = "psci";
48 			operating-points-v2 = <&cluster0_opp>;
53 			compatible = "arm,cortex-a72", "arm,armv8";
56 			enable-method = "psci";
57 			operating-points-v2 = <&cluster0_opp>;
62 			compatible = "arm,cortex-a53", "arm,armv8";
65 			enable-method = "psci";
66 			operating-points-v2 = <&cluster1_opp>;
71 			compatible = "arm,cortex-a53", "arm,armv8";
74 			enable-method = "psci";
75 			operating-points-v2 = <&cluster1_opp>;
80 		compatible = "operating-points-v2";
81 		opp-shared;
83 		opp-250000000 {
84 			opp-hz = /bits/ 64 <250000000>;
85 			clock-latency-ns = <300>;
87 		opp-275000000 {
88 			opp-hz = /bits/ 64 <275000000>;
89 			clock-latency-ns = <300>;
91 		opp-500000000 {
92 			opp-hz = /bits/ 64 <500000000>;
93 			clock-latency-ns = <300>;
95 		opp-550000000 {
96 			opp-hz = /bits/ 64 <550000000>;
97 			clock-latency-ns = <300>;
99 		opp-666667000 {
100 			opp-hz = /bits/ 64 <666667000>;
101 			clock-latency-ns = <300>;
103 		opp-733334000 {
104 			opp-hz = /bits/ 64 <733334000>;
105 			clock-latency-ns = <300>;
107 		opp-1000000000 {
108 			opp-hz = /bits/ 64 <1000000000>;
109 			clock-latency-ns = <300>;
111 		opp-1100000000 {
112 			opp-hz = /bits/ 64 <1100000000>;
113 			clock-latency-ns = <300>;
118 		compatible = "operating-points-v2";
119 		opp-shared;
121 		opp-250000000 {
122 			opp-hz = /bits/ 64 <250000000>;
123 			clock-latency-ns = <300>;
125 		opp-275000000 {
126 			opp-hz = /bits/ 64 <275000000>;
127 			clock-latency-ns = <300>;
129 		opp-500000000 {
130 			opp-hz = /bits/ 64 <500000000>;
131 			clock-latency-ns = <300>;
133 		opp-550000000 {
134 			opp-hz = /bits/ 64 <550000000>;
135 			clock-latency-ns = <300>;
137 		opp-666667000 {
138 			opp-hz = /bits/ 64 <666667000>;
139 			clock-latency-ns = <300>;
141 		opp-733334000 {
142 			opp-hz = /bits/ 64 <733334000>;
143 			clock-latency-ns = <300>;
145 		opp-1000000000 {
146 			opp-hz = /bits/ 64 <1000000000>;
147 			clock-latency-ns = <300>;
149 		opp-1100000000 {
150 			opp-hz = /bits/ 64 <1100000000>;
151 			clock-latency-ns = <300>;
156 		compatible = "arm,psci-1.0";
162 			compatible = "fixed-clock";
163 			#clock-cells = <0>;
164 			clock-frequency = <25000000>;
169 		compatible = "arm,armv8-timer";
177 		compatible = "simple-bus";
178 		#address-cells = <1>;
179 		#size-cells = <1>;
183 			compatible = "socionext,uniphier-uart";
187 			pinctrl-names = "default";
188 			pinctrl-0 = <&pinctrl_uart0>;
190 			clock-frequency = <58820000>;
194 			compatible = "socionext,uniphier-uart";
198 			pinctrl-names = "default";
199 			pinctrl-0 = <&pinctrl_uart1>;
201 			clock-frequency = <58820000>;
205 			compatible = "socionext,uniphier-uart";
209 			pinctrl-names = "default";
210 			pinctrl-0 = <&pinctrl_uart2>;
212 			clock-frequency = <58820000>;
216 			compatible = "socionext,uniphier-uart";
220 			pinctrl-names = "default";
221 			pinctrl-0 = <&pinctrl_uart3>;
223 			clock-frequency = <58820000>;
227 			compatible = "socionext,uniphier-fi2c";
230 			#address-cells = <1>;
231 			#size-cells = <0>;
233 			pinctrl-names = "default";
234 			pinctrl-0 = <&pinctrl_i2c0>;
236 			clock-frequency = <100000>;
240 			compatible = "socionext,uniphier-fi2c";
243 			#address-cells = <1>;
244 			#size-cells = <0>;
246 			pinctrl-names = "default";
247 			pinctrl-0 = <&pinctrl_i2c1>;
249 			clock-frequency = <100000>;
253 			compatible = "socionext,uniphier-fi2c";
255 			#address-cells = <1>;
256 			#size-cells = <0>;
259 			clock-frequency = <400000>;
263 			compatible = "socionext,uniphier-fi2c";
266 			#address-cells = <1>;
267 			#size-cells = <0>;
269 			pinctrl-names = "default";
270 			pinctrl-0 = <&pinctrl_i2c3>;
272 			clock-frequency = <100000>;
276 			compatible = "socionext,uniphier-fi2c";
279 			#address-cells = <1>;
280 			#size-cells = <0>;
282 			pinctrl-names = "default";
283 			pinctrl-0 = <&pinctrl_i2c4>;
285 			clock-frequency = <100000>;
289 			compatible = "socionext,uniphier-fi2c";
291 			#address-cells = <1>;
292 			#size-cells = <0>;
295 			clock-frequency = <400000>;
298 		system_bus: system-bus@58c00000 {
299 			compatible = "socionext,uniphier-system-bus";
302 			#address-cells = <2>;
303 			#size-cells = <1>;
304 			pinctrl-names = "default";
305 			pinctrl-0 = <&pinctrl_system_bus>;
309 			compatible = "socionext,uniphier-smpctrl";
314 			compatible = "socionext,uniphier-ld20-sdctrl",
315 				     "simple-mfd", "syscon";
319 				compatible = "socionext,uniphier-ld20-sd-clock";
320 				#clock-cells = <1>;
324 				compatible = "socionext,uniphier-ld20-sd-reset";
325 				#reset-cells = <1>;
330 			compatible = "socionext,uniphier-ld20-perictrl",
331 				     "simple-mfd", "syscon";
335 				compatible = "socionext,uniphier-ld20-peri-clock";
336 				#clock-cells = <1>;
340 				compatible = "socionext,uniphier-ld20-peri-reset";
341 				#reset-cells = <1>;
346 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
349 			pinctrl-names = "default";
350 			pinctrl-0 = <&pinctrl_emmc_1v8>;
352 			bus-width = <8>;
353 			mmc-ddr-1_8v;
354 			mmc-hs200-1_8v;
355 			cdns,phy-input-delay-legacy = <4>;
356 			cdns,phy-input-delay-mmc-highspeed = <2>;
357 			cdns,phy-input-delay-mmc-ddr = <3>;
358 			cdns,phy-dll-delay-sdclk = <21>;
359 			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
363 			compatible = "socionext,uniphier-sdhc";
367 			pinctrl-names = "default";
368 			pinctrl-0 = <&pinctrl_sd>;
370 			reset-names = "host";
372 			bus-width = <4>;
373 			cap-sd-highspeed;
376 		soc-glue@5f800000 {
377 			compatible = "socionext,uniphier-ld20-soc-glue",
378 				     "simple-mfd", "syscon";
382 				compatible = "socionext,uniphier-ld20-pinctrl";
387 			compatible = "socionext,uniphier-ld20-aidet";
389 			interrupt-controller;
390 			#interrupt-cells = <2>;
393 		gic: interrupt-controller@5fe00000 {
394 			compatible = "arm,gic-v3";
397 			interrupt-controller;
398 			#interrupt-cells = <3>;
403 			compatible = "socionext,uniphier-ld20-sysctrl",
404 				     "simple-mfd", "syscon";
408 				compatible = "socionext,uniphier-ld20-clock";
409 				#clock-cells = <1>;
413 				compatible = "socionext,uniphier-ld20-reset";
414 				#reset-cells = <1>;
418 				compatible = "socionext,uniphier-wdt";
423 			compatible = "socionext,uniphier-ld20-dwc3";
425 			#address-cells = <1>;
426 			#size-cells = <1>;
428 			pinctrl-names = "default";
429 			pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
436 				tx-fifo-resize;
441 			compatible = "socionext,uniphier-denali-nand-v5b";
443 			reg-names = "nand_data", "denali_reg";
446 			pinctrl-names = "default";
447 			pinctrl-0 = <&pinctrl_nand>;
453 #include "uniphier-pinctrl.dtsi"