arm/dts/uniphier-ld11.dtsi

2  * Device Tree Source for UniPhier LD11 SoC
7  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 	compatible = "socionext,uniphier-ld11";
14 	#address-cells = <2>;
15 	#size-cells = <2>;
16 	interrupt-parent = <&gic>;
19 		#address-cells = <2>;
20 		#size-cells = <0>;
22 		cpu-map {
35 			compatible = "arm,cortex-a53", "arm,armv8";
38 			enable-method = "psci";
39 			operating-points-v2 = <&cluster0_opp>;
44 			compatible = "arm,cortex-a53", "arm,armv8";
47 			enable-method = "psci";
48 			operating-points-v2 = <&cluster0_opp>;
53 		compatible = "operating-points-v2";
54 		opp-shared;
56 		opp-245000000 {
57 			opp-hz = /bits/ 64 <245000000>;
58 			clock-latency-ns = <300>;
60 		opp-250000000 {
61 			opp-hz = /bits/ 64 <250000000>;
62 			clock-latency-ns = <300>;
64 		opp-490000000 {
65 			opp-hz = /bits/ 64 <490000000>;
66 			clock-latency-ns = <300>;
68 		opp-500000000 {
69 			opp-hz = /bits/ 64 <500000000>;
70 			clock-latency-ns = <300>;
72 		opp-653334000 {
73 			opp-hz = /bits/ 64 <653334000>;
74 			clock-latency-ns = <300>;
76 		opp-666667000 {
77 			opp-hz = /bits/ 64 <666667000>;
78 			clock-latency-ns = <300>;
80 		opp-980000000 {
81 			opp-hz = /bits/ 64 <980000000>;
82 			clock-latency-ns = <300>;
87 		compatible = "arm,psci-1.0";
93 			compatible = "fixed-clock";
94 			#clock-cells = <0>;
95 			clock-frequency = <25000000>;
100 		compatible = "arm,armv8-timer";
108 		compatible = "simple-bus";
109 		#address-cells = <1>;
110 		#size-cells = <1>;
114 			compatible = "socionext,uniphier-uart";
118 			pinctrl-names = "default";
119 			pinctrl-0 = <&pinctrl_uart0>;
121 			clock-frequency = <58820000>;
125 			compatible = "socionext,uniphier-uart";
129 			pinctrl-names = "default";
130 			pinctrl-0 = <&pinctrl_uart1>;
132 			clock-frequency = <58820000>;
136 			compatible = "socionext,uniphier-uart";
140 			pinctrl-names = "default";
141 			pinctrl-0 = <&pinctrl_uart2>;
143 			clock-frequency = <58820000>;
147 			compatible = "socionext,uniphier-uart";
151 			pinctrl-names = "default";
152 			pinctrl-0 = <&pinctrl_uart3>;
154 			clock-frequency = <58820000>;
158 			compatible = "socionext,uniphier-fi2c";
161 			#address-cells = <1>;
162 			#size-cells = <0>;
164 			pinctrl-names = "default";
165 			pinctrl-0 = <&pinctrl_i2c0>;
167 			clock-frequency = <100000>;
171 			compatible = "socionext,uniphier-fi2c";
174 			#address-cells = <1>;
175 			#size-cells = <0>;
177 			pinctrl-names = "default";
178 			pinctrl-0 = <&pinctrl_i2c1>;
180 			clock-frequency = <100000>;
184 			compatible = "socionext,uniphier-fi2c";
186 			#address-cells = <1>;
187 			#size-cells = <0>;
190 			clock-frequency = <400000>;
194 			compatible = "socionext,uniphier-fi2c";
197 			#address-cells = <1>;
198 			#size-cells = <0>;
200 			pinctrl-names = "default";
201 			pinctrl-0 = <&pinctrl_i2c3>;
203 			clock-frequency = <100000>;
207 			compatible = "socionext,uniphier-fi2c";
210 			#address-cells = <1>;
211 			#size-cells = <0>;
213 			pinctrl-names = "default";
214 			pinctrl-0 = <&pinctrl_i2c4>;
216 			clock-frequency = <100000>;
220 			compatible = "socionext,uniphier-fi2c";
222 			#address-cells = <1>;
223 			#size-cells = <0>;
226 			clock-frequency = <400000>;
229 		system_bus: system-bus@58c00000 {
230 			compatible = "socionext,uniphier-system-bus";
233 			#address-cells = <2>;
234 			#size-cells = <1>;
235 			pinctrl-names = "default";
236 			pinctrl-0 = <&pinctrl_system_bus>;
240 			compatible = "socionext,uniphier-smpctrl";
245 			compatible = "socionext,uniphier-ld11-sdctrl",
246 				     "simple-mfd", "syscon";
250 				compatible = "socionext,uniphier-ld11-sd-reset";
251 				#reset-cells = <1>;
256 			compatible = "socionext,uniphier-ld11-perictrl",
257 				     "simple-mfd", "syscon";
261 				compatible = "socionext,uniphier-ld11-peri-clock";
262 				#clock-cells = <1>;
266 				compatible = "socionext,uniphier-ld11-peri-reset";
267 				#reset-cells = <1>;
272 			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
275 			pinctrl-names = "default";
276 			pinctrl-0 = <&pinctrl_emmc_1v8>;
278 			bus-width = <8>;
279 			mmc-ddr-1_8v;
280 			mmc-hs200-1_8v;
281 			cdns,phy-input-delay-legacy = <4>;
282 			cdns,phy-input-delay-mmc-highspeed = <2>;
283 			cdns,phy-input-delay-mmc-ddr = <3>;
284 			cdns,phy-dll-delay-sdclk = <21>;
285 			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
289 			compatible = "socionext,uniphier-ehci", "generic-ehci";
293 			pinctrl-names = "default";
294 			pinctrl-0 = <&pinctrl_usb0>;
301 			compatible = "socionext,uniphier-ehci", "generic-ehci";
305 			pinctrl-names = "default";
306 			pinctrl-0 = <&pinctrl_usb1>;
313 			compatible = "socionext,uniphier-ehci", "generic-ehci";
317 			pinctrl-names = "default";
318 			pinctrl-0 = <&pinctrl_usb2>;
325 			compatible = "socionext,uniphier-ld11-mioctrl",
326 				     "simple-mfd", "syscon";
330 				compatible = "socionext,uniphier-ld11-mio-clock";
331 				#clock-cells = <1>;
335 				compatible = "socionext,uniphier-ld11-mio-reset";
336 				#reset-cells = <1>;
341 		soc-glue@5f800000 {
342 			compatible = "socionext,uniphier-ld11-soc-glue",
343 				     "simple-mfd", "syscon";
347 				compatible = "socionext,uniphier-ld11-pinctrl";
352 			compatible = "socionext,uniphier-ld11-aidet";
354 			interrupt-controller;
355 			#interrupt-cells = <2>;
358 		gic: interrupt-controller@5fe00000 {
359 			compatible = "arm,gic-v3";
362 			interrupt-controller;
363 			#interrupt-cells = <3>;
368 			compatible = "socionext,uniphier-ld11-sysctrl",
369 				     "simple-mfd", "syscon";
373 				compatible = "socionext,uniphier-ld11-clock";
374 				#clock-cells = <1>;
378 				compatible = "socionext,uniphier-ld11-reset";
379 				#reset-cells = <1>;
383 				compatible = "socionext,uniphier-wdt";
388 			compatible = "socionext,uniphier-denali-nand-v5b";
390 			reg-names = "nand_data", "denali_reg";
393 			pinctrl-names = "default";
394 			pinctrl-0 = <&pinctrl_nand>;
400 #include "uniphier-pinctrl.dtsi"