Lines Matching +full:0 +full:x5a000000
10 /memreserve/ 0x80000000 0x02000000;
20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
45 reg = <0 0x001>;
94 #clock-cells = <0>;
107 soc@0 {
111 ranges = <0 0 0 0xffffffff>;
116 reg = <0x54006800 0x40>;
117 interrupts = <0 33 4>;
119 pinctrl-0 = <&pinctrl_uart0>;
120 clocks = <&peri_clk 0>;
127 reg = <0x54006900 0x40>;
128 interrupts = <0 35 4>;
130 pinctrl-0 = <&pinctrl_uart1>;
138 reg = <0x54006a00 0x40>;
139 interrupts = <0 37 4>;
141 pinctrl-0 = <&pinctrl_uart2>;
149 reg = <0x54006b00 0x40>;
150 interrupts = <0 177 4>;
152 pinctrl-0 = <&pinctrl_uart3>;
160 reg = <0x58780000 0x80>;
162 #size-cells = <0>;
163 interrupts = <0 41 4>;
165 pinctrl-0 = <&pinctrl_i2c0>;
173 reg = <0x58781000 0x80>;
175 #size-cells = <0>;
176 interrupts = <0 42 4>;
178 pinctrl-0 = <&pinctrl_i2c1>;
185 reg = <0x58782000 0x80>;
187 #size-cells = <0>;
188 interrupts = <0 43 4>;
196 reg = <0x58783000 0x80>;
198 #size-cells = <0>;
199 interrupts = <0 44 4>;
201 pinctrl-0 = <&pinctrl_i2c3>;
209 reg = <0x58784000 0x80>;
211 #size-cells = <0>;
212 interrupts = <0 45 4>;
214 pinctrl-0 = <&pinctrl_i2c4>;
221 reg = <0x58785000 0x80>;
223 #size-cells = <0>;
224 interrupts = <0 25 4>;
232 reg = <0x58c00000 0x400>;
236 pinctrl-0 = <&pinctrl_system_bus>;
241 reg = <0x59801000 0x400>;
247 reg = <0x59810000 0x400>;
258 reg = <0x59820000 0x200>;
273 reg = <0x5a000000 0x400>;
274 interrupts = <0 78 4>;
276 pinctrl-0 = <&pinctrl_emmc_1v8>;
291 reg = <0x5a800100 0x100>;
292 interrupts = <0 243 4>;
294 pinctrl-0 = <&pinctrl_usb0>;
303 reg = <0x5a810100 0x100>;
304 interrupts = <0 244 4>;
306 pinctrl-0 = <&pinctrl_usb1>;
315 reg = <0x5a820100 0x100>;
316 interrupts = <0 245 4>;
318 pinctrl-0 = <&pinctrl_usb2>;
327 reg = <0x5b3e0000 0x800>;
344 reg = <0x5f800000 0x2000>;
353 reg = <0x5fc20000 0x200>;
360 reg = <0x5fe00000 0x10000>, /* GICD */
361 <0x5fe40000 0x80000>; /* GICR */
370 reg = <0x61840000 0x10000>;
391 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
392 interrupts = <0 65 4>;
394 pinctrl-0 = <&pinctrl_nand>;