arm/dts/tegra186.dtsi

2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/power/tegra186-powergate.h>
7 #include <dt-bindings/reset/tegra186-reset.h>
10 	compatible = "nvidia,tegra186";
11 	interrupt-parent = <&gic>;
12 	#address-cells = <2>;
13 	#size-cells = <2>;
16 		compatible = "nvidia,tegra186-gpio";
17 		reg-names = "security", "gpio";
28 		gpio-controller;
29 		#gpio-cells = <2>;
30 		interrupt-controller;
31 		#interrupt-cells = <2>;
35 		compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10";
38 		clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
39 			<&bpmp TEGRA186_CLK_EQOS_AXI>,
40 			<&bpmp TEGRA186_CLK_EQOS_RX>,
41 			<&bpmp TEGRA186_CLK_EQOS_PTP_REF>,
42 			<&bpmp TEGRA186_CLK_EQOS_TX>;
43 		clock-names = "slave_bus",
48 		resets = <&bpmp TEGRA186_RESET_EQOS>;
49 		reset-names = "eqos";
50 		phy-mode = "rgmii";
55 		compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
57 		reg-shift = <2>;
62 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
65 		#address-cells = <1>;
66 		#size-cells = <0>;
67 		clocks = <&bpmp TEGRA186_CLK_I2C1>;
68 		clock-names = "div-clk";
69 		resets = <&bpmp TEGRA186_RESET_I2C1>;
70 		reset-names = "i2c";
75 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
78 		#address-cells = <1>;
79 		#size-cells = <0>;
80 		clocks = <&bpmp TEGRA186_CLK_I2C3>;
81 		clock-names = "div-clk";
82 		resets = <&bpmp TEGRA186_RESET_I2C3>;
83 		reset-names = "i2c";
88 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
91 		#address-cells = <1>;
92 		#size-cells = <0>;
93 		clocks = <&bpmp TEGRA186_CLK_I2C4>;
94 		clock-names = "div-clk";
95 		resets = <&bpmp TEGRA186_RESET_I2C4>;
96 		reset-names = "i2c";
101 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
104 		#address-cells = <1>;
105 		#size-cells = <0>;
106 		clocks = <&bpmp TEGRA186_CLK_I2C6>;
107 		clock-names = "div-clk";
108 		resets = <&bpmp TEGRA186_RESET_I2C6>;
109 		reset-names = "i2c";
114 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
117 		#address-cells = <1>;
118 		#size-cells = <0>;
119 		clocks = <&bpmp TEGRA186_CLK_I2C7>;
120 		clock-names = "div-clk";
121 		resets = <&bpmp TEGRA186_RESET_I2C7>;
122 		reset-names = "i2c";
127 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
130 		#address-cells = <1>;
131 		#size-cells = <0>;
132 		clocks = <&bpmp TEGRA186_CLK_I2C9>;
133 		clock-names = "div-clk";
134 		resets = <&bpmp TEGRA186_RESET_I2C9>;
135 		reset-names = "i2c";
140 		compatible = "nvidia,tegra186-sdhci";
142 		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
143 		reset-names = "sdhci";
144 		clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
150 		compatible = "nvidia,tegra186-sdhci";
152 		resets = <&bpmp TEGRA186_RESET_SDMMC4>;
153 		reset-names = "sdhci";
154 		clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
159 	gic: interrupt-controller@3881000 {
160 		compatible = "arm,gic-400";
161 		#interrupt-cells = <3>;
162 		interrupt-controller;
169 		interrupt-parent = <&gic>;
173 		compatible = "nvidia,tegra186-hsp";
176 		interrupt-names = "doorbell";
177 		#mbox-cells = <2>;
181 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
184 		#address-cells = <1>;
185 		#size-cells = <0>;
186 		clocks = <&bpmp TEGRA186_CLK_I2C2>;
187 		clock-names = "div-clk";
188 		resets = <&bpmp TEGRA186_RESET_I2C2>;
189 		reset-names = "i2c";
194 		compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
197 		#address-cells = <1>;
198 		#size-cells = <0>;
199 		clocks = <&bpmp TEGRA186_CLK_I2C8>;
200 		clock-names = "div-clk";
201 		resets = <&bpmp TEGRA186_RESET_I2C8>;
202 		reset-names = "i2c";
207 		compatible = "nvidia,tegra186-gpio-aon";
208 		reg-names = "security", "gpio";
214 		gpio-controller;
215 		#gpio-cells = <2>;
216 		interrupt-controller;
217 		#interrupt-cells = <2>;
220 	pcie-controller@10003000 {
221 		compatible = "nvidia,tegra186-pcie";
226 		reg-names = "pads", "afi", "cs";
230 		interrupt-names = "intr", "msi", "wake";
232 		#interrupt-cells = <1>;
233 		interrupt-map-mask = <0 0 0 0>;
234 		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
236 		bus-range = <0x00 0xff>;
237 		#address-cells = <3>;
238 		#size-cells = <2>;
244 			  0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000   /* non-prefetchable memory (127 MiB) */
247 		clocks = <&bpmp TEGRA186_CLK_PCIE>,
248 			 <&bpmp TEGRA186_CLK_AFI>;
249 		clock-names = "pex", "afi";
250 		resets = <&bpmp TEGRA186_RESET_PCIE>,
251 			 <&bpmp TEGRA186_RESET_AFI>,
252 			 <&bpmp TEGRA186_RESET_PCIEXCLK>;
253 		reset-names = "pex", "afi", "pcie_x";
254 		power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
259 			assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
263 			#address-cells = <3>;
264 			#size-cells = <2>;
267 			nvidia,num-lanes = <2>;
272 			assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
276 			#address-cells = <3>;
277 			#size-cells = <2>;
280 			nvidia,num-lanes = <1>;
285 			assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
289 			#address-cells = <3>;
290 			#size-cells = <2>;
293 			nvidia,num-lanes = <1>;
298 		compatible = "nvidia,tegra186-sysram", "mmio-sram";
300 		#address-cells = <2>;
301 		#size-cells = <2>;
305 			compatible = "nvidia,tegra186-bpmp-shmem";
310 			compatible = "nvidia,tegra186-bpmp-shmem";
315 	bpmp: bpmp {  label
316 		compatible = "nvidia,tegra186-bpmp";
320 		 * node these reference point at, are board-specific, since
321 		 * they depend on the BCT's memory carve-out setup, the
322 		 * firmware that's actually loaded onto the BPMP, etc. However,
326 		#clock-cells = <1>;
327 		#power-domain-cells = <1>;
328 		#reset-cells = <1>;
331 			compatible = "nvidia,tegra186-bpmp-i2c";
332 			nvidia,bpmp-bus-id = <5>;
333 			#address-cells = <1>;
334 			#size-cells = <0>;