arm/dts/sun9i-a80.dtsi

2  * Copyright 2014 Chen-Yu Tsai
4  * Chen-Yu Tsai <wens@csie.org>
6  * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 	interrupt-parent = <&gic>;
55 		#address-cells = <1>;
56 		#size-cells = <0>;
59 			compatible = "arm,cortex-a7";
65 			compatible = "arm,cortex-a7";
71 			compatible = "arm,cortex-a7";
77 			compatible = "arm,cortex-a7";
83 			compatible = "arm,cortex-a15";
89 			compatible = "arm,cortex-a15";
95 			compatible = "arm,cortex-a15";
101 			compatible = "arm,cortex-a15";
113 		compatible = "arm,armv7-timer";
118 		clock-frequency = <24000000>;
119 		arm,cpu-registers-not-fw-configured;
123 		#address-cells = <1>;
124 		#size-cells = <1>;
132 		 * This clock is actually configurable from the PRCM address
134 		 * the clock switched to an internal 16M RC oscillator. Under
137 		 * as a fixed clock. Also it is not entirely clear if the
138 		 * osc24M mux in the PRCM affects the entire clock tree, which
139 		 * would also throw all the PLL clock rates off, or just the
143 			#clock-cells = <0>;
144 			compatible = "fixed-clock";
145 			clock-frequency = <24000000>;
146 			clock-output-names = "osc24M";
150 		 * The 32k clock is from an external source, normally the
151 		 * AC100 codec/RTC chip. This clock is by default enabled
157 			#clock-cells = <0>;
158 			compatible = "fixed-clock";
159 			clock-frequency = <32768>;
160 			clock-output-names = "osc32k";
164 			#clock-cells = <1>;
165 			#reset-cells = <1>;
166 			compatible = "allwinner,sun9i-a80-usb-mod-clk";
169 			clock-output-names = "usb0_ahb", "usb_ohci0",
175 			#clock-cells = <1>;
176 			#reset-cells = <1>;
177 			compatible = "allwinner,sun9i-a80-usb-phy-clk";
180 			clock-output-names = "usb_phy0", "usb_hsic1_480M",
187 			#clock-cells = <0>;
188 			compatible = "fixed-clock";
189 			clock-rate = <0>;
190 			clock-output-names = "pll3";
194 			#clock-cells = <0>;
195 			compatible = "allwinner,sun9i-a80-pll4-clk";
198 			clock-output-names = "pll4";
202 			#clock-cells = <0>;
203 			compatible = "allwinner,sun9i-a80-pll4-clk";
206 			clock-output-names = "pll12";
210 			#clock-cells = <0>;
211 			compatible = "allwinner,sun9i-a80-gt-clk";
214 			clock-output-names = "gt";
218 			#clock-cells = <0>;
219 			compatible = "allwinner,sun9i-a80-ahb-clk";
222 			clock-output-names = "ahb0";
226 			#clock-cells = <0>;
227 			compatible = "allwinner,sun9i-a80-ahb-clk";
230 			clock-output-names = "ahb1";
234 			#clock-cells = <0>;
235 			compatible = "allwinner,sun9i-a80-ahb-clk";
238 			clock-output-names = "ahb2";
242 			#clock-cells = <0>;
243 			compatible = "allwinner,sun9i-a80-apb0-clk";
246 			clock-output-names = "apb0";
250 			#clock-cells = <0>;
251 			compatible = "allwinner,sun9i-a80-apb1-clk";
254 			clock-output-names = "apb1";
258 			#clock-cells = <0>;
259 			compatible = "allwinner,sun9i-a80-gt-clk";
262 			clock-output-names = "cci400";
266 			#clock-cells = <1>;
267 			compatible = "allwinner,sun9i-a80-mmc-clk";
270 			clock-output-names = "mmc0", "mmc0_output",
275 			#clock-cells = <1>;
276 			compatible = "allwinner,sun9i-a80-mmc-clk";
279 			clock-output-names = "mmc1", "mmc1_output",
284 			#clock-cells = <1>;
285 			compatible = "allwinner,sun9i-a80-mmc-clk";
288 			clock-output-names = "mmc2", "mmc2_output",
293 			#clock-cells = <1>;
294 			compatible = "allwinner,sun9i-a80-mmc-clk";
297 			clock-output-names = "mmc3", "mmc3_output",
302 			#clock-cells = <1>;
303 			compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
306 			clock-indices = <0>, <1>, <3>,
312 			clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
321 			#clock-cells = <1>;
322 			compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
325 			clock-indices = <0>, <1>,
329 			clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
336 			#clock-cells = <1>;
337 			compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
340 			clock-indices = <0>, <1>,
343 			clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
349 			#clock-cells = <1>;
350 			compatible = "allwinner,sun9i-a80-apb0-gates-clk";
353 			clock-indices = <1>, <5>,
357 			clock-output-names = "apb0_spdif", "apb0_pio",
364 			#clock-cells = <1>;
365 			compatible = "allwinner,sun9i-a80-apb1-gates-clk";
368 			clock-indices = <0>, <1>,
373 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
381 			compatible = "allwinner,sun9i-a80-cpus-clk";
383 			#clock-cells = <0>;
385 			clock-output-names = "cpus";
389 			compatible = "fixed-factor-clock";
390 			#clock-cells = <0>;
391 			clock-div = <1>;
392 			clock-mult = <1>;
394 			clock-output-names = "ahbs";
398 			compatible = "allwinner,sun8i-a23-apb0-clk";
400 			#clock-cells = <0>;
402 			clock-output-names = "apbs";
406 			compatible = "allwinner,sun9i-a80-apbs-gates-clk";
408 			#clock-cells = <1>;
410 			clock-indices = <0>, <1>,
417 			clock-output-names = "apbs_pio", "apbs_ir",
428 			#clock-cells = <0>;
429 			compatible = "allwinner,sun4i-a10-mod0-clk";
431 			clock-output-names = "r_1wire";
436 			#clock-cells = <0>;
437 			compatible = "allwinner,sun4i-a10-mod0-clk";
439 			clock-output-names = "r_ir";
444 		compatible = "simple-bus";
445 		#address-cells = <1>;
446 		#size-cells = <1>;
454 			compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
460 			phy-names = "usb";
465 			compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
471 			phy-names = "usb";
476 			compatible = "allwinner,sun9i-a80-usb-phy";
479 			clock-names = "phy";
481 			reset-names = "phy";
483 			#phy-cells = <0>;
487 			compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
493 			phy-names = "usb";
498 			compatible = "allwinner,sun9i-a80-usb-phy";
502 			clock-names = "hsic_480M", "hsic_12M", "phy";
504 			reset-names = "hsic", "phy";
506 			#phy-cells = <0>;
512 			compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
518 			phy-names = "usb";
523 			compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
529 			phy-names = "usb";
534 			compatible = "allwinner,sun9i-a80-usb-phy";
538 			clock-names = "hsic_480M", "hsic_12M", "phy";
540 			reset-names = "hsic", "phy";
542 			#phy-cells = <0>;
546 			compatible = "allwinner,sun9i-a80-mmc";
550 			clock-names = "ahb", "mmc", "output", "sample";
552 			reset-names = "ahb";
555 			#address-cells = <1>;
556 			#size-cells = <0>;
560 			compatible = "allwinner,sun9i-a80-mmc";
564 			clock-names = "ahb", "mmc", "output", "sample";
566 			reset-names = "ahb";
569 			#address-cells = <1>;
570 			#size-cells = <0>;
574 			compatible = "allwinner,sun9i-a80-mmc";
578 			clock-names = "ahb", "mmc", "output", "sample";
580 			reset-names = "ahb";
583 			#address-cells = <1>;
584 			#size-cells = <0>;
588 			compatible = "allwinner,sun9i-a80-mmc";
592 			clock-names = "ahb", "mmc", "output", "sample";
594 			reset-names = "ahb";
597 			#address-cells = <1>;
598 			#size-cells = <0>;
602 			compatible = "allwinner,sun9i-a80-mmc-config-clk";
605 			clock-names = "ahb";
607 			reset-names = "ahb";
608 			#clock-cells = <1>;
609 			#reset-cells = <1>;
610 			clock-output-names = "mmc0_config", "mmc1_config",
614 		gic: interrupt-controller@01c41000 {
615 			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
620 			interrupt-controller;
621 			#interrupt-cells = <3>;
626 			#reset-cells = <1>;
627 			compatible = "allwinner,sun6i-a31-clock-reset";
632 			#reset-cells = <1>;
633 			compatible = "allwinner,sun6i-a31-clock-reset";
638 			#reset-cells = <1>;
639 			compatible = "allwinner,sun6i-a31-clock-reset";
644 			#reset-cells = <1>;
645 			compatible = "allwinner,sun6i-a31-clock-reset";
650 			#reset-cells = <1>;
651 			compatible = "allwinner,sun6i-a31-clock-reset";
656 			compatible = "allwinner,sun4i-a10-timer";
669 			compatible = "allwinner,sun6i-a31-wdt";
675 			compatible = "allwinner,sun9i-a80-pinctrl";
683 			gpio-controller;
684 			interrupt-controller;
685 			#interrupt-cells = <3>;
686 			#size-cells = <0>;
687 			#gpio-cells = <3>;
738 			compatible = "snps,dw-apb-uart";
741 			reg-shift = <2>;
742 			reg-io-width = <4>;
749 			compatible = "snps,dw-apb-uart";
752 			reg-shift = <2>;
753 			reg-io-width = <4>;
760 			compatible = "snps,dw-apb-uart";
763 			reg-shift = <2>;
764 			reg-io-width = <4>;
771 			compatible = "snps,dw-apb-uart";
774 			reg-shift = <2>;
775 			reg-io-width = <4>;
782 			compatible = "snps,dw-apb-uart";
785 			reg-shift = <2>;
786 			reg-io-width = <4>;
793 			compatible = "snps,dw-apb-uart";
796 			reg-shift = <2>;
797 			reg-io-width = <4>;
804 			compatible = "allwinner,sun6i-a31-i2c";
810 			#address-cells = <1>;
811 			#size-cells = <0>;
815 			compatible = "allwinner,sun6i-a31-i2c";
821 			#address-cells = <1>;
822 			#size-cells = <0>;
826 			compatible = "allwinner,sun6i-a31-i2c";
832 			#address-cells = <1>;
833 			#size-cells = <0>;
837 			compatible = "allwinner,sun6i-a31-i2c";
843 			#address-cells = <1>;
844 			#size-cells = <0>;
848 			compatible = "allwinner,sun6i-a31-i2c";
854 			#address-cells = <1>;
855 			#size-cells = <0>;
859 			compatible = "allwinner,sun6i-a31-wdt";
866 			compatible = "allwinner,sun6i-a31-clock-reset";
867 			#reset-cells = <1>;
870 		nmi_intc: interrupt-controller@080015a0 {
871 			compatible = "allwinner,sun9i-a80-nmi";
872 			interrupt-controller;
873 			#interrupt-cells = <2>;
879 			compatible = "allwinner,sun5i-a13-ir";
881 			pinctrl-names = "default";
882 			pinctrl-0 = <&r_ir_pins>;
884 			clock-names = "apb", "ir";
891 			compatible = "snps,dw-apb-uart";
894 			reg-shift = <2>;
895 			reg-io-width = <4>;
902 			compatible = "allwinner,sun9i-a80-r-pinctrl";
908 			gpio-controller;
909 			interrupt-controller;
910 			#address-cells = <1>;
911 			#size-cells = <0>;
912 			#gpio-cells = <3>;
930 			compatible = "allwinner,sun8i-a23-rsb";
934 			clock-frequency = <3000000>;
936 			pinctrl-names = "default";
937 			pinctrl-0 = <&r_rsb_pins>;
939 			#address-cells = <1>;
940 			#size-cells = <0>;