arm/dts/sun9i-a80.dtsi

55 		#address-cells = <1>;
64 		cpu1: cpu@1 {
123 		#address-cells = <1>;
124 		#size-cells = <1>;
164 			#clock-cells = <1>;
165 			#reset-cells = <1>;
168 			clocks = <&ahb1_gates 1>;
175 			#clock-cells = <1>;
176 			#reset-cells = <1>;
179 			clocks = <&ahb1_gates 1>;
266 			#clock-cells = <1>;
275 			#clock-cells = <1>;
284 			#clock-cells = <1>;
293 			#clock-cells = <1>;
302 			#clock-cells = <1>;
306 			clock-indices = <0>, <1>, <3>,
321 			#clock-cells = <1>;
325 			clock-indices = <0>, <1>,
336 			#clock-cells = <1>;
340 			clock-indices = <0>, <1>,
349 			#clock-cells = <1>;
353 			clock-indices = <1>, <5>,
364 			#clock-cells = <1>;
368 			clock-indices = <0>, <1>,
391 			clock-div = <1>;
392 			clock-mult = <1>;
408 			#clock-cells = <1>;
410 			clock-indices = <0>, <1>,
445 		#address-cells = <1>;
446 		#size-cells = <1>;
457 			clocks = <&usb_mod_clk 1>;
468 			clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>;
478 			clocks = <&usb_phy_clk 1>;
549 				 <&mmc0_clk 1>, <&mmc0_clk 2>;
555 			#address-cells = <1>;
562 			clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
563 				 <&mmc1_clk 1>, <&mmc1_clk 2>;
565 			resets = <&mmc_config_clk 1>;
569 			#address-cells = <1>;
577 				 <&mmc2_clk 1>, <&mmc2_clk 2>;
583 			#address-cells = <1>;
591 				 <&mmc3_clk 1>, <&mmc3_clk 2>;
597 			#address-cells = <1>;
601 		mmc_config_clk: clk@01c13000 {
608 			#clock-cells = <1>;
609 			#reset-cells = <1>;
626 			#reset-cells = <1>;
632 			#reset-cells = <1>;
638 			#reset-cells = <1>;
644 			#reset-cells = <1>;
650 			#reset-cells = <1>;
751 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
810 			#address-cells = <1>;
818 			clocks = <&apb1_gates 1>;
819 			resets = <&apb1_resets 1>;
821 			#address-cells = <1>;
832 			#address-cells = <1>;
843 			#address-cells = <1>;
854 			#address-cells = <1>;
867 			#reset-cells = <1>;
883 			clocks = <&apbs_gates 1>, <&r_ir_clk>;
885 			resets = <&apbs_rst 1>;
910 			#address-cells = <1>;
939 			#address-cells = <1>;