Lines Matching +full:0 +full:x01c13000
56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
67 reg = <0x1>;
73 reg = <0x2>;
79 reg = <0x3>;
85 reg = <0x100>;
91 reg = <0x101>;
97 reg = <0x102>;
103 reg = <0x103>;
109 reg = <0 0x20000000 0x02 0>;
129 ranges = <0 0 0 0x20000000>;
143 #clock-cells = <0>;
157 #clock-cells = <0>;
167 reg = <0x00a08000 0x4>;
178 reg = <0x00a08004 0x4>;
187 #clock-cells = <0>;
189 clock-rate = <0>;
194 #clock-cells = <0>;
196 reg = <0x0600000c 0x4>;
202 #clock-cells = <0>;
204 reg = <0x0600002c 0x4>;
210 #clock-cells = <0>;
212 reg = <0x0600005c 0x4>;
218 #clock-cells = <0>;
220 reg = <0x06000060 0x4>;
226 #clock-cells = <0>;
228 reg = <0x06000064 0x4>;
234 #clock-cells = <0>;
236 reg = <0x06000068 0x4>;
242 #clock-cells = <0>;
244 reg = <0x06000070 0x4>;
250 #clock-cells = <0>;
252 reg = <0x06000074 0x4>;
258 #clock-cells = <0>;
260 reg = <0x06000078 0x4>;
268 reg = <0x06000410 0x4>;
277 reg = <0x06000414 0x4>;
286 reg = <0x06000418 0x4>;
295 reg = <0x0600041c 0x4>;
304 reg = <0x06000580 0x4>;
306 clock-indices = <0>, <1>, <3>,
323 reg = <0x06000584 0x4>;
325 clock-indices = <0>, <1>,
338 reg = <0x06000588 0x4>;
340 clock-indices = <0>, <1>,
351 reg = <0x06000590 0x4>;
366 reg = <0x06000594 0x4>;
368 clock-indices = <0>, <1>,
382 reg = <0x08001410 0x4>;
383 #clock-cells = <0>;
390 #clock-cells = <0>;
399 reg = <0x0800141c 0x4>;
400 #clock-cells = <0>;
407 reg = <0x08001428 0x4>;
410 clock-indices = <0>, <1>,
427 reg = <0x08001450 0x4>;
428 #clock-cells = <0>;
435 reg = <0x08001454 0x4>;
436 #clock-cells = <0>;
451 ranges = <0 0 0 0x20000000>;
455 reg = <0x00a00000 0x100>;
466 reg = <0x00a00400 0x100>;
477 reg = <0x00a00800 0x4>;
483 #phy-cells = <0>;
488 reg = <0x00a01000 0x100>;
499 reg = <0x00a01800 0x4>;
506 #phy-cells = <0>;
513 reg = <0x00a02000 0x100>;
524 reg = <0x00a02400 0x100>;
535 reg = <0x00a02800 0x4>;
542 #phy-cells = <0>;
547 reg = <0x01c0f000 0x1000>;
548 clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>,
551 resets = <&mmc_config_clk 0>;
556 #size-cells = <0>;
561 reg = <0x01c10000 0x1000>;
562 clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>,
570 #size-cells = <0>;
575 reg = <0x01c11000 0x1000>;
576 clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>,
584 #size-cells = <0>;
589 reg = <0x01c12000 0x1000>;
590 clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>,
598 #size-cells = <0>;
603 reg = <0x01c13000 0x10>;
616 reg = <0x01c41000 0x1000>,
617 <0x01c42000 0x1000>,
618 <0x01c44000 0x2000>,
619 <0x01c46000 0x2000>;
628 reg = <0x060005a0 0x4>;
634 reg = <0x060005a4 0x4>;
640 reg = <0x060005a8 0x4>;
646 reg = <0x060005b0 0x4>;
652 reg = <0x060005b4 0x4>;
657 reg = <0x06000c00 0xa0>;
670 reg = <0x06000ca0 0x20>;
676 reg = <0x06000800 0x400>;
686 #size-cells = <0>;
689 i2c3_pins_a: i2c3@0 {
722 uart0_pins_a: uart0@0 {
729 uart4_pins_a: uart4@0 {
739 reg = <0x07000000 0x400>;
740 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
750 reg = <0x07000400 0x400>;
761 reg = <0x07000800 0x400>;
772 reg = <0x07000c00 0x400>;
783 reg = <0x07001000 0x400>;
794 reg = <0x07001400 0x400>;
805 reg = <0x07002800 0x400>;
807 clocks = <&apb1_gates 0>;
808 resets = <&apb1_resets 0>;
811 #size-cells = <0>;
816 reg = <0x07002c00 0x400>;
822 #size-cells = <0>;
827 reg = <0x07003000 0x400>;
833 #size-cells = <0>;
838 reg = <0x07003400 0x400>;
844 #size-cells = <0>;
849 reg = <0x07003800 0x400>;
855 #size-cells = <0>;
860 reg = <0x08001000 0x20>;
865 reg = <0x080014b0 0x4>;
874 reg = <0x080015a0 0xc>;
882 pinctrl-0 = <&r_ir_pins>;
886 reg = <0x08002000 0x40>;
892 reg = <0x08002800 0x400>;
903 reg = <0x08002c00 0x400>;
906 clocks = <&apbs_gates 0>;
907 resets = <&apbs_rst 0>;
911 #size-cells = <0>;
931 reg = <0x08003400 0x400>;
937 pinctrl-0 = <&r_rsb_pins>;
940 #size-cells = <0>;