arm/dts/sun8i-h3.dtsi

59 		#size-cells = <0>;
61 		cpu@0 {
64 			reg = <0>;
100 			#clock-cells = <0>;
107 			#clock-cells = <0>;
115 			#clock-cells = <0>;
125 			reg = <0x01f01428 0x4>;
128 			clock-indices = <0>, <1>;
134 			reg = <0x01f01454 0x4>;
135 			#clock-cells = <0>;
149 			reg = <0x01c00000 0x34>;
154 			reg = <0x01c02000 0x1000>;
164 			reg = <0x01c0f000 0x1000>;
178 			#size-cells = <0>;
184 			reg = <0x01c10000 0x1000>;
198 			#size-cells = <0>;
204 			reg = <0x01c11000 0x1000>;
218 			#size-cells = <0>;
223 			reg = <0x01c19400 0x2c>,
224 			      <0x01c1a800 0x4>,
225 			      <0x01c1b800 0x4>,
226 			      <0x01c1c800 0x4>,
227 			      <0x01c1d800 0x4>;
255 			reg = <0x01c1b000 0x100>;
266 			reg = <0x01c1b400 0x100>;
278 			reg = <0x01c1c000 0x100>;
289 			reg = <0x01c1c400 0x100>;
301 			reg = <0x01c1d000 0x100>;
312 			reg = <0x01c1d400 0x100>;
324 			reg = <0x01c20000 0x400>;
333 			reg = <0x01c20800 0x400>;
342 			emac_rgmii_pins: emac0@0 {
353 			mmc0_pins_a: mmc0@0 {
361 			mmc0_cd_pin: mmc0_cd_pin@0 {
368 			mmc1_pins_a: mmc1@0 {
386 			uart0_pins_a: uart0@0 {
393 			uart1_pins_a: uart1@0 {
403 			reg = <0x01c20c00 0xa0>;
411 			reg = <0x01c20ca0 0x20>;
417 			reg = <0x01c28000 0x400>;
418 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
430 			reg = <0x01c28400 0x400>;
443 			reg = <0x01c28800 0x400>;
456 			reg = <0x01c28c00 0x400>;
469 			reg = <0x01c30000 0x104>, <0x01c00030 0x4>;
477 			#size-cells = <0>;
483 			reg = <0x01c81000 0x1000>,
484 			      <0x01c82000 0x1000>,
485 			      <0x01c84000 0x2000>,
486 			      <0x01c86000 0x2000>;
494 			reg = <0x01f00000 0x54>;
500 			reg = <0x01f014b0 0x4>;
511 			reg = <0x01f02000 0x40>;
517 			reg = <0x01f02c00 0x400>;
519 			clocks = <&apb0_gates 0>;
520 			resets = <&apb0_reset 0>;
526 			ir_pins_a: ir@0 {