arm/dts/sun8i-a23-a33.dtsi

59 		simplefb_lcd: framebuffer@0 {
63 			clocks = <&pll6 0>;
81 		#size-cells = <0>;
83 		cpu@0 {
86 			reg = <0>;
102 			#clock-cells = <0>;
109 			#clock-cells = <0>;
116 			#clock-cells = <0>;
118 			reg = <0x01c20000 0x4>;
125 			#clock-cells = <0>;
127 			clock-frequency = <0>;
134 			reg = <0x01c20028 0x4>;
140 			#clock-cells = <0>;
142 			reg = <0x01c20050 0x4>;
155 			#clock-cells = <0>;
157 			reg = <0x01c20050 0x4>;
163 			#clock-cells = <0>;
165 			reg = <0x01c20054 0x4>;
166 			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
171 			#clock-cells = <0>;
173 			reg = <0x01c20054 0x4>;
181 			reg = <0x01c20068 0x4>;
183 			clock-indices = <0>, <5>,
190 			#clock-cells = <0>;
192 			reg = <0x01c20058 0x4>;
193 			clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
200 			reg = <0x01c2006c 0x4>;
202 			clock-indices = <0>, <1>,
215 			reg = <0x01c20088 0x4>;
216 			clocks = <&osc24M>, <&pll6 0>;
225 			reg = <0x01c2008c 0x4>;
226 			clocks = <&osc24M>, <&pll6 0>;
235 			reg = <0x01c20090 0x4>;
236 			clocks = <&osc24M>, <&pll6 0>;
246 			reg = <0x01c200cc 0x4>;
261 			reg = <0x01c02000 0x1000>;
271 			reg = <0x01c0f000 0x1000>;
273 				 <&mmc0_clk 0>,
285 			#size-cells = <0>;
291 			reg = <0x01c10000 0x1000>;
293 				 <&mmc1_clk 0>,
305 			#size-cells = <0>;
311 			reg = <0x01c11000 0x1000>;
313 				 <&mmc2_clk 0>,
325 			#size-cells = <0>;
330 			reg = <0x01c1a000 0x100>;
341 			reg = <0x01c1a400 0x100>;
352 			reg = <0x01c20800 0x400>;
360 			uart0_pins_a: uart0@0 {
367 			mmc0_pins_a: mmc0@0 {
375 			mmc1_pins_a: mmc1@0 {
400 			i2c0_pins_a: i2c0@0 {
407 			i2c1_pins_a: i2c1@0 {
414 			i2c2_pins_a: i2c2@0 {
425 			reg = <0x01c202c0 0xc>;
431 			reg = <0x01c202d0 0x4>;
437 			reg = <0x01c202d8 0x4>;
442 			reg = <0x01c20c00 0xa0>;
450 			reg = <0x01c20ca0 0x20>;
456 			reg = <0x01c21400 0xc>;
464 			reg = <0x01c22800 0x100>;
471 			reg = <0x01c28000 0x400>;
472 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
484 			reg = <0x01c28400 0x400>;
497 			reg = <0x01c28800 0x400>;
510 			reg = <0x01c28c00 0x400>;
523 			reg = <0x01c29000 0x400>;
536 			reg = <0x01c2ac00 0x400>;
538 			clocks = <&apb2_gates 0>;
539 			resets = <&apb2_rst 0>;
542 			#size-cells = <0>;
547 			reg = <0x01c2b000 0x400>;
553 			#size-cells = <0>;
558 			reg = <0x01c2b400 0x400>;
564 			#size-cells = <0>;
569 			reg = <0x01c81000 0x1000>,
570 			      <0x01c82000 0x1000>,
571 			      <0x01c84000 0x2000>,
572 			      <0x01c86000 0x2000>;
580 			reg = <0x01f00000 0x54>;
589 			reg = <0x01f00c0c 0x38>;
595 			reg = <0x01f01400 0x200>;
599 				#clock-cells = <0>;
608 				#clock-cells = <0>;
617 				#clock-cells = <0>;
639 			reg = <0x01f01c00 0x300>;
644 			reg = <0x01f02800 0x400>;
655 			reg = <0x01f02c00 0x400>;
657 			clocks = <&apb0_gates 0>;
658 			resets = <&apb0_rst 0>;
663 			#size-cells = <0>;
673 			r_uart_pins_a: r_uart@0 {
683 			reg = <0x01f03400 0x400>;
689 			pinctrl-0 = <&r_rsb_pins>;
692 			#size-cells = <0>;