Lines Matching full:pll6
259 pll6: clk@01c20028 { label
261 compatible = "allwinner,sun4i-a10-pll6-clk";
264 clock-output-names = "pll6_sata", "pll6_other", "pll6",
297 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
316 * Use PLL6 as parent, instead of CPU/AXI
320 assigned-clock-parents = <&pll6 3>;
383 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
572 clocks = <&pll6 1>;
581 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
727 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
1050 clocks = <&pll6 0>, <&ahb_gates 25>;