Lines Matching +full:clk +full:- +full:pins
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
51 #include <dt-bindings/dma/sun4i-a10.h>
52 #include <dt-bindings/pinctrl/sun4i-a10.h>
55 interrupt-parent = <&gic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
99 #address-cells = <1>;
100 #size-cells = <0>;
103 compatible = "arm,cortex-a7";
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
118 #cooling-cells = <2>;
119 cooling-min-level = <0>;
120 cooling-max-level = <6>;
124 compatible = "arm,cortex-a7";
130 thermal-zones {
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
137 cooling-maps {
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
167 compatible = "arm,armv7-timer";
175 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
181 #address-cells = <1>;
182 #size-cells = <1>;
185 osc24M: clk@01c20050 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-osc-clk";
189 clock-frequency = <24000000>;
190 clock-output-names = "osc24M";
194 #clock-cells = <0>;
195 compatible = "fixed-factor-clock";
196 clock-div = <8>;
197 clock-mult = <1>;
199 clock-output-names = "osc3M";
202 osc32k: clk@0 {
203 #clock-cells = <0>;
204 compatible = "fixed-clock";
205 clock-frequency = <32768>;
206 clock-output-names = "osc32k";
209 pll1: clk@01c20000 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-a10-pll1-clk";
214 clock-output-names = "pll1";
217 pll2: clk@01c20008 {
218 #clock-cells = <1>;
219 compatible = "allwinner,sun4i-a10-pll2-clk";
222 clock-output-names = "pll2-1x", "pll2-2x",
223 "pll2-4x", "pll2-8x";
226 pll3: clk@01c20010 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-a10-pll3-clk";
231 clock-output-names = "pll3";
235 #clock-cells = <0>;
236 compatible = "fixed-factor-clock";
238 clock-div = <1>;
239 clock-mult = <2>;
240 clock-output-names = "pll3-2x";
243 pll4: clk@01c20018 {
244 #clock-cells = <0>;
245 compatible = "allwinner,sun7i-a20-pll4-clk";
248 clock-output-names = "pll4";
251 pll5: clk@01c20020 {
252 #clock-cells = <1>;
253 compatible = "allwinner,sun4i-a10-pll5-clk";
256 clock-output-names = "pll5_ddr", "pll5_other";
259 pll6: clk@01c20028 {
260 #clock-cells = <1>;
261 compatible = "allwinner,sun4i-a10-pll6-clk";
264 clock-output-names = "pll6_sata", "pll6_other", "pll6",
268 pll7: clk@01c20030 {
269 #clock-cells = <0>;
270 compatible = "allwinner,sun4i-a10-pll3-clk";
273 clock-output-names = "pll7";
277 #clock-cells = <0>;
278 compatible = "fixed-factor-clock";
280 clock-div = <1>;
281 clock-mult = <2>;
282 clock-output-names = "pll7-2x";
285 pll8: clk@01c20040 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun7i-a20-pll4-clk";
290 clock-output-names = "pll8";
294 #clock-cells = <0>;
295 compatible = "allwinner,sun4i-a10-cpu-clk";
298 clock-output-names = "cpu";
302 #clock-cells = <0>;
303 compatible = "allwinner,sun4i-a10-axi-clk";
306 clock-output-names = "axi";
310 #clock-cells = <0>;
311 compatible = "allwinner,sun5i-a13-ahb-clk";
314 clock-output-names = "ahb";
319 assigned-clocks = <&ahb>;
320 assigned-clock-parents = <&pll6 3>;
323 ahb_gates: clk@01c20060 {
324 #clock-cells = <1>;
325 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
328 clock-indices = <0>, <1>,
341 clock-output-names = "ahb_usb0", "ahb_ehci0",
357 #clock-cells = <0>;
358 compatible = "allwinner,sun4i-a10-apb0-clk";
361 clock-output-names = "apb0";
364 apb0_gates: clk@01c20068 {
365 #clock-cells = <1>;
366 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
369 clock-indices = <0>, <1>,
373 clock-output-names = "apb0_codec", "apb0_spdif",
379 apb1: clk@01c20058 {
380 #clock-cells = <0>;
381 compatible = "allwinner,sun4i-a10-apb1-clk";
384 clock-output-names = "apb1";
387 apb1_gates: clk@01c2006c {
388 #clock-cells = <1>;
389 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
392 clock-indices = <0>, <1>,
398 clock-output-names = "apb1_i2c0", "apb1_i2c1",
406 nand_clk: clk@01c20080 {
407 #clock-cells = <0>;
408 compatible = "allwinner,sun4i-a10-mod0-clk";
411 clock-output-names = "nand";
414 ms_clk: clk@01c20084 {
415 #clock-cells = <0>;
416 compatible = "allwinner,sun4i-a10-mod0-clk";
419 clock-output-names = "ms";
422 mmc0_clk: clk@01c20088 {
423 #clock-cells = <1>;
424 compatible = "allwinner,sun4i-a10-mmc-clk";
427 clock-output-names = "mmc0",
432 mmc1_clk: clk@01c2008c {
433 #clock-cells = <1>;
434 compatible = "allwinner,sun4i-a10-mmc-clk";
437 clock-output-names = "mmc1",
442 mmc2_clk: clk@01c20090 {
443 #clock-cells = <1>;
444 compatible = "allwinner,sun4i-a10-mmc-clk";
447 clock-output-names = "mmc2",
452 mmc3_clk: clk@01c20094 {
453 #clock-cells = <1>;
454 compatible = "allwinner,sun4i-a10-mmc-clk";
457 clock-output-names = "mmc3",
462 ts_clk: clk@01c20098 {
463 #clock-cells = <0>;
464 compatible = "allwinner,sun4i-a10-mod0-clk";
467 clock-output-names = "ts";
470 ss_clk: clk@01c2009c {
471 #clock-cells = <0>;
472 compatible = "allwinner,sun4i-a10-mod0-clk";
475 clock-output-names = "ss";
478 spi0_clk: clk@01c200a0 {
479 #clock-cells = <0>;
480 compatible = "allwinner,sun4i-a10-mod0-clk";
483 clock-output-names = "spi0";
486 spi1_clk: clk@01c200a4 {
487 #clock-cells = <0>;
488 compatible = "allwinner,sun4i-a10-mod0-clk";
491 clock-output-names = "spi1";
494 spi2_clk: clk@01c200a8 {
495 #clock-cells = <0>;
496 compatible = "allwinner,sun4i-a10-mod0-clk";
499 clock-output-names = "spi2";
502 pata_clk: clk@01c200ac {
503 #clock-cells = <0>;
504 compatible = "allwinner,sun4i-a10-mod0-clk";
507 clock-output-names = "pata";
510 ir0_clk: clk@01c200b0 {
511 #clock-cells = <0>;
512 compatible = "allwinner,sun4i-a10-mod0-clk";
515 clock-output-names = "ir0";
518 ir1_clk: clk@01c200b4 {
519 #clock-cells = <0>;
520 compatible = "allwinner,sun4i-a10-mod0-clk";
523 clock-output-names = "ir1";
526 i2s0_clk: clk@01c200b8 {
527 #clock-cells = <0>;
528 compatible = "allwinner,sun4i-a10-mod1-clk";
534 clock-output-names = "i2s0";
537 ac97_clk: clk@01c200bc {
538 #clock-cells = <0>;
539 compatible = "allwinner,sun4i-a10-mod1-clk";
545 clock-output-names = "ac97";
548 spdif_clk: clk@01c200c0 {
549 #clock-cells = <0>;
550 compatible = "allwinner,sun4i-a10-mod1-clk";
556 clock-output-names = "spdif";
559 keypad_clk: clk@01c200c4 {
560 #clock-cells = <0>;
561 compatible = "allwinner,sun4i-a10-mod0-clk";
564 clock-output-names = "keypad";
567 usb_clk: clk@01c200cc {
568 #clock-cells = <1>;
569 #reset-cells = <1>;
570 compatible = "allwinner,sun4i-a10-usb-clk";
573 clock-output-names = "usb_ohci0", "usb_ohci1",
577 spi3_clk: clk@01c200d4 {
578 #clock-cells = <0>;
579 compatible = "allwinner,sun4i-a10-mod0-clk";
582 clock-output-names = "spi3";
585 i2s1_clk: clk@01c200d8 {
586 #clock-cells = <0>;
587 compatible = "allwinner,sun4i-a10-mod1-clk";
593 clock-output-names = "i2s1";
596 i2s2_clk: clk@01c200dc {
597 #clock-cells = <0>;
598 compatible = "allwinner,sun4i-a10-mod1-clk";
604 clock-output-names = "i2s2";
607 dram_gates: clk@01c20100 {
608 #clock-cells = <1>;
609 compatible = "allwinner,sun4i-a10-dram-gates-clk";
612 clock-indices = <0>,
621 clock-output-names = "dram_ve",
632 de_be0_clk: clk@01c20104 {
633 #clock-cells = <0>;
634 #reset-cells = <0>;
635 compatible = "allwinner,sun4i-a10-display-clk";
638 clock-output-names = "de-be0";
641 de_be1_clk: clk@01c20108 {
642 #clock-cells = <0>;
643 #reset-cells = <0>;
644 compatible = "allwinner,sun4i-a10-display-clk";
647 clock-output-names = "de-be1";
650 de_fe0_clk: clk@01c2010c {
651 #clock-cells = <0>;
652 #reset-cells = <0>;
653 compatible = "allwinner,sun4i-a10-display-clk";
656 clock-output-names = "de-fe0";
659 de_fe1_clk: clk@01c20110 {
660 #clock-cells = <0>;
661 #reset-cells = <0>;
662 compatible = "allwinner,sun4i-a10-display-clk";
665 clock-output-names = "de-fe1";
668 tcon0_ch0_clk: clk@01c20118 {
669 #clock-cells = <0>;
670 #reset-cells = <1>;
671 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
674 clock-output-names = "tcon0-ch0-sclk";
678 tcon1_ch0_clk: clk@01c2011c {
679 #clock-cells = <0>;
680 #reset-cells = <1>;
681 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
684 clock-output-names = "tcon1-ch0-sclk";
688 tcon0_ch1_clk: clk@01c2012c {
689 #clock-cells = <0>;
690 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
693 clock-output-names = "tcon0-ch1-sclk";
697 tcon1_ch1_clk: clk@01c20130 {
698 #clock-cells = <0>;
699 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
702 clock-output-names = "tcon1-ch1-sclk";
706 ve_clk: clk@01c2013c {
707 #clock-cells = <0>;
708 #reset-cells = <0>;
709 compatible = "allwinner,sun4i-a10-ve-clk";
712 clock-output-names = "ve";
715 codec_clk: clk@01c20140 {
716 #clock-cells = <0>;
717 compatible = "allwinner,sun4i-a10-codec-clk";
720 clock-output-names = "codec";
723 mbus_clk: clk@01c2015c {
724 #clock-cells = <0>;
725 compatible = "allwinner,sun5i-a13-mbus-clk";
728 clock-output-names = "mbus";
735 * mode, using clk_set_rate auto-reparenting.
740 mii_phy_tx_clk: clk@2 {
741 #clock-cells = <0>;
742 compatible = "fixed-clock";
743 clock-frequency = <25000000>;
744 clock-output-names = "mii_phy_tx";
747 gmac_int_tx_clk: clk@3 {
748 #clock-cells = <0>;
749 compatible = "fixed-clock";
750 clock-frequency = <125000000>;
751 clock-output-names = "gmac_int_tx";
754 gmac_tx_clk: clk@01c20164 {
755 #clock-cells = <0>;
756 compatible = "allwinner,sun7i-a20-gmac-clk";
759 clock-output-names = "gmac_tx";
765 osc24M_32k: clk@1 {
766 #clock-cells = <0>;
767 compatible = "fixed-factor-clock";
768 clock-div = <750>;
769 clock-mult = <1>;
771 clock-output-names = "osc24M_32k";
774 clk_out_a: clk@01c201f0 {
775 #clock-cells = <0>;
776 compatible = "allwinner,sun7i-a20-out-clk";
779 clock-output-names = "clk_out_a";
782 clk_out_b: clk@01c201f4 {
783 #clock-cells = <0>;
784 compatible = "allwinner,sun7i-a20-out-clk";
787 clock-output-names = "clk_out_b";
792 compatible = "simple-bus";
793 #address-cells = <1>;
794 #size-cells = <1>;
797 sram-controller@01c00000 {
798 compatible = "allwinner,sun4i-a10-sram-controller";
800 #address-cells = <1>;
801 #size-cells = <1>;
805 compatible = "mmio-sram";
807 #address-cells = <1>;
808 #size-cells = <1>;
811 emac_sram: sram-section@8000 {
812 compatible = "allwinner,sun4i-a10-sram-a3-a4";
819 compatible = "mmio-sram";
821 #address-cells = <1>;
822 #size-cells = <1>;
825 otg_sram: sram-section@0000 {
826 compatible = "allwinner,sun4i-a10-sram-d";
833 nmi_intc: interrupt-controller@01c00030 {
834 compatible = "allwinner,sun7i-a20-sc-nmi";
835 interrupt-controller;
836 #interrupt-cells = <2>;
841 dma: dma-controller@01c02000 {
842 compatible = "allwinner,sun4i-a10-dma";
846 #dma-cells = <2>;
850 compatible = "allwinner,sun4i-a10-nand";
854 clock-names = "ahb", "mod";
856 dma-names = "rxtx";
858 #address-cells = <1>;
859 #size-cells = <0>;
863 compatible = "allwinner,sun4i-a10-spi";
867 clock-names = "ahb", "mod";
870 dma-names = "rx", "tx";
872 #address-cells = <1>;
873 #size-cells = <0>;
877 compatible = "allwinner,sun4i-a10-spi";
881 clock-names = "ahb", "mod";
884 dma-names = "rx", "tx";
886 #address-cells = <1>;
887 #size-cells = <0>;
891 compatible = "allwinner,sun4i-a10-emac";
900 compatible = "allwinner,sun4i-a10-mdio";
903 #address-cells = <1>;
904 #size-cells = <0>;
908 compatible = "allwinner,sun7i-a20-mmc",
909 "allwinner,sun5i-a13-mmc";
915 clock-names = "ahb",
921 #address-cells = <1>;
922 #size-cells = <0>;
926 compatible = "allwinner,sun7i-a20-mmc",
927 "allwinner,sun5i-a13-mmc";
933 clock-names = "ahb",
939 #address-cells = <1>;
940 #size-cells = <0>;
944 compatible = "allwinner,sun7i-a20-mmc",
945 "allwinner,sun5i-a13-mmc";
951 clock-names = "ahb",
957 #address-cells = <1>;
958 #size-cells = <0>;
962 compatible = "allwinner,sun7i-a20-mmc",
963 "allwinner,sun5i-a13-mmc";
969 clock-names = "ahb",
975 #address-cells = <1>;
976 #size-cells = <0>;
980 compatible = "allwinner,sun4i-a10-musb";
984 interrupt-names = "mc";
986 phy-names = "usb";
993 #phy-cells = <1>;
994 compatible = "allwinner,sun7i-a20-usb-phy";
996 reg-names = "phy_ctrl", "pmu1", "pmu2";
998 clock-names = "usb_phy";
1000 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
1005 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1010 phy-names = "usb";
1015 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1020 phy-names = "usb";
1024 crypto: crypto-engine@01c15000 {
1025 compatible = "allwinner,sun4i-a10-crypto";
1029 clock-names = "ahb", "mod";
1033 compatible = "allwinner,sun4i-a10-spi";
1037 clock-names = "ahb", "mod";
1040 dma-names = "rx", "tx";
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1047 compatible = "allwinner,sun4i-a10-ahci";
1055 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1060 phy-names = "usb";
1065 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1070 phy-names = "usb";
1075 compatible = "allwinner,sun4i-a10-spi";
1079 clock-names = "ahb", "mod";
1082 dma-names = "rx", "tx";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1089 compatible = "allwinner,sun7i-a20-pinctrl";
1093 gpio-controller;
1094 interrupt-controller;
1095 #interrupt-cells = <3>;
1096 #gpio-cells = <3>;
1099 allwinner,pins = "PI12";
1106 allwinner,pins = "PI13";
1113 allwinner,pins = "PA0", "PA1", "PA2",
1124 allwinner,pins = "PA0", "PA1", "PA2",
1135 allwinner,pins = "PA0", "PA1", "PA2",
1150 allwinner,pins = "PB0", "PB1";
1157 allwinner,pins = "PB18", "PB19";
1164 allwinner,pins = "PB20", "PB21";
1171 allwinner,pins = "PI0", "PI1";
1178 allwinner,pins = "PB4";
1185 allwinner,pins = "PB3";
1192 allwinner,pins = "PB23";
1199 allwinner,pins = "PB22";
1206 allwinner,pins = "PF0", "PF1", "PF2",
1214 allwinner,pins = "PH1";
1221 allwinner,pins = "PC6", "PC7", "PC8",
1229 allwinner,pins = "PI4", "PI5", "PI6",
1237 allwinner,pins = "PI20", "PI21";
1244 allwinner,pins = "PH12", "PH13";
1251 allwinner,pins = "PB2";
1258 allwinner,pins = "PI3";
1265 allwinner,pins = "PB13";
1272 allwinner,pins = "PI11", "PI12", "PI13";
1279 allwinner,pins = "PI10";
1286 allwinner,pins = "PI14";
1293 allwinner,pins = "PI17", "PI18", "PI19";
1300 allwinner,pins = "PI16";
1307 allwinner,pins = "PC20", "PC21", "PC22";
1314 allwinner,pins = "PB15", "PB16", "PB17";
1321 allwinner,pins = "PC19";
1328 allwinner,pins = "PB14";
1335 allwinner,pins = "PB22", "PB23";
1342 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
1349 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
1356 allwinner,pins = "PH0", "PH1";
1363 allwinner,pins = "PG10", "PG11";
1370 allwinner,pins = "PH4", "PH5";
1377 allwinner,pins = "PI10", "PI11";
1384 allwinner,pins = "PI12", "PI13";
1391 allwinner,pins = "PI20", "PI21";
1399 compatible = "allwinner,sun4i-a10-timer";
1411 compatible = "allwinner,sun4i-a10-wdt";
1416 compatible = "allwinner,sun7i-a20-rtc";
1422 compatible = "allwinner,sun7i-a20-pwm";
1425 #pwm-cells = <3>;
1430 #sound-dai-cells = <0>;
1431 compatible = "allwinner,sun4i-a10-spdif";
1435 clock-names = "apb", "spdif";
1438 dma-names = "rx", "tx";
1443 compatible = "allwinner,sun4i-a10-ir";
1445 clock-names = "apb", "ir";
1452 compatible = "allwinner,sun4i-a10-ir";
1454 clock-names = "apb", "ir";
1461 #sound-dai-cells = <0>;
1462 compatible = "allwinner,sun4i-a10-i2s";
1466 clock-names = "apb", "mod";
1469 dma-names = "rx", "tx";
1474 #sound-dai-cells = <0>;
1475 compatible = "allwinner,sun4i-a10-i2s";
1479 clock-names = "apb", "mod";
1482 dma-names = "rx", "tx";
1487 compatible = "allwinner,sun4i-a10-lradc-keys";
1494 #sound-dai-cells = <0>;
1495 compatible = "allwinner,sun7i-a20-codec";
1499 clock-names = "apb", "codec";
1502 dma-names = "rx", "tx";
1507 compatible = "allwinner,sun7i-a20-sid";
1512 #sound-dai-cells = <0>;
1513 compatible = "allwinner,sun4i-a10-i2s";
1517 clock-names = "apb", "mod";
1520 dma-names = "rx", "tx";
1525 compatible = "allwinner,sun5i-a13-ts";
1528 #thermal-sensor-cells = <0>;
1532 compatible = "snps,dw-apb-uart";
1535 reg-shift = <2>;
1536 reg-io-width = <4>;
1542 compatible = "snps,dw-apb-uart";
1545 reg-shift = <2>;
1546 reg-io-width = <4>;
1552 compatible = "snps,dw-apb-uart";
1555 reg-shift = <2>;
1556 reg-io-width = <4>;
1562 compatible = "snps,dw-apb-uart";
1565 reg-shift = <2>;
1566 reg-io-width = <4>;
1572 compatible = "snps,dw-apb-uart";
1575 reg-shift = <2>;
1576 reg-io-width = <4>;
1582 compatible = "snps,dw-apb-uart";
1585 reg-shift = <2>;
1586 reg-io-width = <4>;
1592 compatible = "snps,dw-apb-uart";
1595 reg-shift = <2>;
1596 reg-io-width = <4>;
1602 compatible = "snps,dw-apb-uart";
1605 reg-shift = <2>;
1606 reg-io-width = <4>;
1612 compatible = "allwinner,sun7i-a20-i2c",
1613 "allwinner,sun4i-a10-i2c";
1618 #address-cells = <1>;
1619 #size-cells = <0>;
1623 compatible = "allwinner,sun7i-a20-i2c",
1624 "allwinner,sun4i-a10-i2c";
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1634 compatible = "allwinner,sun7i-a20-i2c",
1635 "allwinner,sun4i-a10-i2c";
1640 #address-cells = <1>;
1641 #size-cells = <0>;
1645 compatible = "allwinner,sun7i-a20-i2c",
1646 "allwinner,sun4i-a10-i2c";
1651 #address-cells = <1>;
1652 #size-cells = <0>;
1656 compatible = "allwinner,sun7i-a20-i2c",
1657 "allwinner,sun4i-a10-i2c";
1662 #address-cells = <1>;
1663 #size-cells = <0>;
1667 compatible = "allwinner,sun7i-a20-gmac";
1670 interrupt-names = "macirq";
1672 clock-names = "stmmaceth", "allwinner_gmac_tx";
1674 snps,fixed-burst;
1677 #address-cells = <1>;
1678 #size-cells = <0>;
1682 compatible = "allwinner,sun7i-a20-hstimer";
1691 gic: interrupt-controller@01c81000 {
1692 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1697 interrupt-controller;
1698 #interrupt-cells = <3>;
1703 compatible = "allwinner,sun4i-a10-ps2";
1711 compatible = "allwinner,sun4i-a10-ps2";