arm/dts/sun7i-a20.dtsi

66 		framebuffer@0 {
100 		#size-cells = <0>;
102 		cpu0: cpu@0 {
105 			reg = <0>;
119 			cooling-min-level = <0>;
163 		reg = <0x40000000 0x80000000>;
186 			#clock-cells = <0>;
188 			reg = <0x01c20050 0x4>;
194 			#clock-cells = <0>;
202 		osc32k: clk@0 {
203 			#clock-cells = <0>;
210 			#clock-cells = <0>;
212 			reg = <0x01c20000 0x4>;
220 			reg = <0x01c20008 0x8>;
227 			#clock-cells = <0>;
229 			reg = <0x01c20010 0x4>;
235 			#clock-cells = <0>;
244 			#clock-cells = <0>;
246 			reg = <0x01c20018 0x4>;
254 			reg = <0x01c20020 0x4>;
262 			reg = <0x01c20028 0x4>;
269 			#clock-cells = <0>;
271 			reg = <0x01c20030 0x4>;
277 			#clock-cells = <0>;
286 			#clock-cells = <0>;
288 			reg = <0x01c20040 0x4>;
294 			#clock-cells = <0>;
296 			reg = <0x01c20054 0x4>;
302 			#clock-cells = <0>;
304 			reg = <0x01c20054 0x4>;
310 			#clock-cells = <0>;
312 			reg = <0x01c20054 0x4>;
326 			reg = <0x01c20060 0x8>;
328 			clock-indices = <0>, <1>,
357 			#clock-cells = <0>;
359 			reg = <0x01c20054 0x4>;
367 			reg = <0x01c20068 0x4>;
369 			clock-indices = <0>, <1>,
380 			#clock-cells = <0>;
382 			reg = <0x01c20058 0x4>;
390 			reg = <0x01c2006c 0x4>;
392 			clock-indices = <0>, <1>,
407 			#clock-cells = <0>;
409 			reg = <0x01c20080 0x4>;
415 			#clock-cells = <0>;
417 			reg = <0x01c20084 0x4>;
425 			reg = <0x01c20088 0x4>;
435 			reg = <0x01c2008c 0x4>;
445 			reg = <0x01c20090 0x4>;
455 			reg = <0x01c20094 0x4>;
463 			#clock-cells = <0>;
465 			reg = <0x01c20098 0x4>;
471 			#clock-cells = <0>;
473 			reg = <0x01c2009c 0x4>;
479 			#clock-cells = <0>;
481 			reg = <0x01c200a0 0x4>;
487 			#clock-cells = <0>;
489 			reg = <0x01c200a4 0x4>;
495 			#clock-cells = <0>;
497 			reg = <0x01c200a8 0x4>;
503 			#clock-cells = <0>;
505 			reg = <0x01c200ac 0x4>;
511 			#clock-cells = <0>;
513 			reg = <0x01c200b0 0x4>;
519 			#clock-cells = <0>;
521 			reg = <0x01c200b4 0x4>;
527 			#clock-cells = <0>;
529 			reg = <0x01c200b8 0x4>;
538 			#clock-cells = <0>;
540 			reg = <0x01c200bc 0x4>;
549 			#clock-cells = <0>;
551 			reg = <0x01c200c0 0x4>;
560 			#clock-cells = <0>;
562 			reg = <0x01c200c4 0x4>;
571 			reg = <0x01c200cc 0x4>;
578 			#clock-cells = <0>;
580 			reg = <0x01c200d4 0x4>;
586 			#clock-cells = <0>;
588 			reg = <0x01c200d8 0x4>;
597 			#clock-cells = <0>;
599 			reg = <0x01c200dc 0x4>;
610 			reg = <0x01c20100 0x4>;
611 			clocks = <&pll5 0>;
612 			clock-indices = <0>,
633 			#clock-cells = <0>;
634 			#reset-cells = <0>;
636 			reg = <0x01c20104 0x4>;
642 			#clock-cells = <0>;
643 			#reset-cells = <0>;
645 			reg = <0x01c20108 0x4>;
651 			#clock-cells = <0>;
652 			#reset-cells = <0>;
654 			reg = <0x01c2010c 0x4>;
660 			#clock-cells = <0>;
661 			#reset-cells = <0>;
663 			reg = <0x01c20110 0x4>;
669 			#clock-cells = <0>;
672 			reg = <0x01c20118 0x4>;
679 			#clock-cells = <0>;
682 			reg = <0x01c2011c 0x4>;
689 			#clock-cells = <0>;
691 			reg = <0x01c2012c 0x4>;
698 			#clock-cells = <0>;
700 			reg = <0x01c20130 0x4>;
707 			#clock-cells = <0>;
708 			#reset-cells = <0>;
710 			reg = <0x01c2013c 0x4>;
716 			#clock-cells = <0>;
718 			reg = <0x01c20140 0x4>;
724 			#clock-cells = <0>;
726 			reg = <0x01c2015c 0x4>;
741 			#clock-cells = <0>;
748 			#clock-cells = <0>;
755 			#clock-cells = <0>;
757 			reg = <0x01c20164 0x4>;
766 			#clock-cells = <0>;
775 			#clock-cells = <0>;
777 			reg = <0x01c201f0 0x4>;
783 			#clock-cells = <0>;
785 			reg = <0x01c201f4 0x4>;
799 			reg = <0x01c00000 0x30>;
806 				reg = <0x00000000 0xc000>;
809 				ranges = <0 0x00000000 0xc000>;
813 					reg = <0x8000 0x4000>;
820 				reg = <0x00010000 0x1000>;
823 				ranges = <0 0x00010000 0x1000>;
827 					reg = <0x0000 0x1000>;
837 			reg = <0x01c00030 0x0c>;
838 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
843 			reg = <0x01c02000 0x1000>;
851 			reg = <0x01c03000 0x1000>;
859 			#size-cells = <0>;
864 			reg = <0x01c05000 0x1000>;
873 			#size-cells = <0>;
878 			reg = <0x01c06000 0x1000>;
887 			#size-cells = <0>;
892 			reg = <0x01c0b000 0x1000>;
901 			reg = <0x01c0b080 0x14>;
904 			#size-cells = <0>;
910 			reg = <0x01c0f000 0x1000>;
912 				 <&mmc0_clk 0>,
922 			#size-cells = <0>;
928 			reg = <0x01c10000 0x1000>;
930 				 <&mmc1_clk 0>,
940 			#size-cells = <0>;
946 			reg = <0x01c11000 0x1000>;
948 				 <&mmc2_clk 0>,
958 			#size-cells = <0>;
964 			reg = <0x01c12000 0x1000>;
966 				 <&mmc3_clk 0>,
976 			#size-cells = <0>;
981 			reg = <0x01c13000 0x0400>;
982 			clocks = <&ahb_gates 0>;
985 			phys = <&usbphy 0>;
987 			extcon = <&usbphy 0>;
995 			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
999 			resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
1006 			reg = <0x01c14000 0x100>;
1016 			reg = <0x01c14400 0x100>;
1026 			reg = <0x01c15000 0x1000>;
1034 			reg = <0x01c17000 0x1000>;
1043 			#size-cells = <0>;
1048 			reg = <0x01c18000 0x1000>;
1050 			clocks = <&pll6 0>, <&ahb_gates 25>;
1056 			reg = <0x01c1c000 0x100>;
1066 			reg = <0x01c1c400 0x100>;
1076 			reg = <0x01c1f000 0x1000>;
1085 			#size-cells = <0>;
1090 			reg = <0x01c20800 0x400>;
1098 			clk_out_a_pins_a: clk_out_a@0 {
1105 			clk_out_b_pins_a: clk_out_b@0 {
1112 			emac_pins_a: emac0@0 {
1123 			gmac_pins_mii_a: gmac_mii@0 {
1134 			gmac_pins_rgmii_a: gmac_rgmii@0 {
1149 			i2c0_pins_a: i2c0@0 {
1156 			i2c1_pins_a: i2c1@0 {
1163 			i2c2_pins_a: i2c2@0 {
1170 			i2c3_pins_a: i2c3@0 {
1177 			ir0_rx_pins_a: ir0@0 {
1191 			ir1_rx_pins_a: ir1@0 {
1205 			mmc0_pins_a: mmc0@0 {
1213 			mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1220 			mmc2_pins_a: mmc2@0 {
1228 			mmc3_pins_a: mmc3@0 {
1236 			ps20_pins_a: ps20@0 {
1243 			ps21_pins_a: ps21@0 {
1250 			pwm0_pins_a: pwm0@0 {
1257 			pwm1_pins_a: pwm1@0 {
1264 			spdif_tx_pins_a: spdif@0 {
1271 			spi0_pins_a: spi0@0 {
1278 			spi0_cs0_pins_a: spi0_cs0@0 {
1285 			spi0_cs1_pins_a: spi0_cs1@0 {
1292 			spi1_pins_a: spi1@0 {
1299 			spi1_cs0_pins_a: spi1_cs0@0 {
1306 			spi2_pins_a: spi2@0 {
1320 			spi2_cs0_pins_a: spi2_cs0@0 {
1334 			uart0_pins_a: uart0@0 {
1341 			uart2_pins_a: uart2@0 {
1348 			uart3_pins_a: uart3@0 {
1362 			uart4_pins_a: uart4@0 {
1376 			uart5_pins_a: uart5@0 {
1383 			uart6_pins_a: uart6@0 {
1390 			uart7_pins_a: uart7@0 {
1400 			reg = <0x01c20c00 0x90>;
1412 			reg = <0x01c20c90 0x10>;
1417 			reg = <0x01c20d00 0x20>;
1423 			reg = <0x01c20e00 0xc>;
1430 			#sound-dai-cells = <0>;
1432 			reg = <0x01c21000 0x400>;
1447 			reg = <0x01c21800 0x40>;
1456 			reg = <0x01c21c00 0x40>;
1461 			#sound-dai-cells = <0>;
1463 			reg = <0x01c22000 0x400>;
1474 			#sound-dai-cells = <0>;
1476 			reg = <0x01c22400 0x400>;
1488 			reg = <0x01c22800 0x100>;
1494 			#sound-dai-cells = <0>;
1496 			reg = <0x01c22c00 0x40>;
1498 			clocks = <&apb0_gates 0>, <&codec_clk>;
1508 			reg = <0x01c23800 0x200>;
1512 			#sound-dai-cells = <0>;
1514 			reg = <0x01c24400 0x400>;
1526 			reg = <0x01c25000 0x100>;
1528 			#thermal-sensor-cells = <0>;
1533 			reg = <0x01c28000 0x400>;
1543 			reg = <0x01c28400 0x400>;
1553 			reg = <0x01c28800 0x400>;
1563 			reg = <0x01c28c00 0x400>;
1573 			reg = <0x01c29000 0x400>;
1583 			reg = <0x01c29400 0x400>;
1593 			reg = <0x01c29800 0x400>;
1603 			reg = <0x01c29c00 0x400>;
1614 			reg = <0x01c2ac00 0x400>;
1616 			clocks = <&apb1_gates 0>;
1619 			#size-cells = <0>;
1625 			reg = <0x01c2b000 0x400>;
1630 			#size-cells = <0>;
1636 			reg = <0x01c2b400 0x400>;
1641 			#size-cells = <0>;
1647 			reg = <0x01c2b800 0x400>;
1652 			#size-cells = <0>;
1658 			reg = <0x01c2c000 0x400>;
1663 			#size-cells = <0>;
1668 			reg = <0x01c50000 0x10000>;
1678 			#size-cells = <0>;
1683 			reg = <0x01c60000 0x1000>;
1693 			reg = <0x01c81000 0x1000>,
1694 			      <0x01c82000 0x1000>,
1695 			      <0x01c84000 0x2000>,
1696 			      <0x01c86000 0x2000>;
1704 			reg = <0x01c2a000 0x400>;
1712 			reg = <0x01c2a400 0x400>;