Lines Matching +full:0 +full:x01c20050
64 simplefb_hdmi: framebuffer@0 {
68 clocks = <&pll6 0>;
76 clocks = <&pll6 0>;
94 #size-cells = <0>;
96 cpu0: cpu@0 {
99 reg = <0>;
110 cooling-min-level = <0>;
166 reg = <0x40000000 0x80000000>;
183 #clock-cells = <0>;
188 osc32k: clk@0 {
189 #clock-cells = <0>;
196 #clock-cells = <0>;
198 reg = <0x01c20000 0x4>;
206 reg = <0x01c20028 0x4>;
212 #clock-cells = <0>;
214 reg = <0x01c20050 0x4>;
227 #clock-cells = <0>;
229 reg = <0x01c20050 0x4>;
235 #clock-cells = <0>;
237 reg = <0x01c20054 0x4>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
247 assigned-clock-parents = <&pll6 0>;
253 reg = <0x01c20060 0x8>;
286 #clock-cells = <0>;
288 reg = <0x01c20054 0x4>;
296 reg = <0x01c20068 0x4>;
298 clock-indices = <0>, <4>,
307 #clock-cells = <0>;
309 reg = <0x01c20058 0x4>;
310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
317 reg = <0x01c2006c 0x4>;
319 clock-indices = <0>, <1>,
333 reg = <0x01c20088 0x4>;
334 clocks = <&osc24M>, <&pll6 0>;
343 reg = <0x01c2008c 0x4>;
344 clocks = <&osc24M>, <&pll6 0>;
353 reg = <0x01c20090 0x4>;
354 clocks = <&osc24M>, <&pll6 0>;
363 reg = <0x01c20094 0x4>;
364 clocks = <&osc24M>, <&pll6 0>;
371 #clock-cells = <0>;
373 reg = <0x01c2009c 0x4>;
374 clocks = <&osc24M>, <&pll6 0>;
379 #clock-cells = <0>;
381 reg = <0x01c200a0 0x4>;
382 clocks = <&osc24M>, <&pll6 0>;
387 #clock-cells = <0>;
389 reg = <0x01c200a4 0x4>;
390 clocks = <&osc24M>, <&pll6 0>;
395 #clock-cells = <0>;
397 reg = <0x01c200a8 0x4>;
398 clocks = <&osc24M>, <&pll6 0>;
403 #clock-cells = <0>;
405 reg = <0x01c200ac 0x4>;
406 clocks = <&osc24M>, <&pll6 0>;
414 reg = <0x01c200cc 0x4>;
434 #clock-cells = <0>;
441 #clock-cells = <0>;
448 #clock-cells = <0>;
450 reg = <0x01c200d0 0x4>;
464 reg = <0x01c02000 0x1000>;
474 reg = <0x01c0f000 0x1000>;
476 <&mmc0_clk 0>,
488 #size-cells = <0>;
494 reg = <0x01c10000 0x1000>;
496 <&mmc1_clk 0>,
508 #size-cells = <0>;
514 reg = <0x01c11000 0x1000>;
516 <&mmc2_clk 0>,
528 #size-cells = <0>;
534 reg = <0x01c12000 0x1000>;
536 <&mmc3_clk 0>,
548 #size-cells = <0>;
553 reg = <0x01c19000 0x0400>;
558 phys = <&usbphy 0>;
560 extcon = <&usbphy 0>;
566 reg = <0x01c19400 0x10>,
567 <0x01c1a800 0x4>,
568 <0x01c1b800 0x4>;
578 resets = <&usb_clk 0>,
590 reg = <0x01c1a000 0x100>;
601 reg = <0x01c1a400 0x100>;
612 reg = <0x01c1b000 0x100>;
623 reg = <0x01c1b400 0x100>;
634 reg = <0x01c1c400 0x100>;
643 reg = <0x01c20800 0x400>;
654 uart0_pins_a: uart0@0 {
661 i2c0_pins_a: i2c0@0 {
668 i2c1_pins_a: i2c1@0 {
675 i2c2_pins_a: i2c2@0 {
682 mmc0_pins_a: mmc0@0 {
690 mmc1_pins_a: mmc1@0 {
698 mmc2_pins_a: mmc2@0 {
726 gmac_pins_mii_a: gmac_mii@0 {
737 gmac_pins_gmii_a: gmac_gmii@0 {
754 gmac_pins_rgmii_a: gmac_rgmii@0 {
772 reg = <0x01c202c0 0xc>;
778 reg = <0x01c202d0 0x4>;
784 reg = <0x01c202d8 0x4>;
789 reg = <0x01c20c00 0xa0>;
800 reg = <0x01c20ca0 0x20>;
805 reg = <0x01c22800 0x100>;
812 reg = <0x01c25000 0x100>;
814 #thermal-sensor-cells = <0>;
819 reg = <0x01c28000 0x400>;
820 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
832 reg = <0x01c28400 0x400>;
845 reg = <0x01c28800 0x400>;
858 reg = <0x01c28c00 0x400>;
871 reg = <0x01c29000 0x400>;
884 reg = <0x01c29400 0x400>;
897 reg = <0x01c2ac00 0x400>;
899 clocks = <&apb2_gates 0>;
900 resets = <&apb2_rst 0>;
903 #size-cells = <0>;
908 reg = <0x01c2b000 0x400>;
914 #size-cells = <0>;
919 reg = <0x01c2b400 0x400>;
925 #size-cells = <0>;
930 reg = <0x01c2b800 0x400>;
936 #size-cells = <0>;
941 reg = <0x01c30000 0x1054>;
953 #size-cells = <0>;
958 reg = <0x01c15000 0x1000>;
969 reg = <0x01c60000 0x1000>;
980 reg = <0x01c68000 0x1000>;
992 reg = <0x01c69000 0x1000>;
1004 reg = <0x01c6a000 0x1000>;
1016 reg = <0x01c6b000 0x1000>;
1028 reg = <0x01c81000 0x1000>,
1029 <0x01c82000 0x1000>,
1030 <0x01c84000 0x2000>,
1031 <0x01c86000 0x2000>;
1039 reg = <0x01f00000 0x54>;
1048 reg = <0x01f00c0c 0x38>;
1054 reg = <0x01f01400 0x200>;
1058 #clock-cells = <0>;
1059 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
1060 <&pll6 0>;
1066 #clock-cells = <0>;
1075 #clock-cells = <0>;
1091 #clock-cells = <0>;
1105 reg = <0x01f01c00 0x300>;
1114 reg = <0x01f02000 0x40>;
1120 reg = <0x01f02c00 0x400>;
1123 clocks = <&apb0_gates 0>;
1124 resets = <&apb0_rst 0>;
1128 #size-cells = <0>;
1131 ir_pins_a: ir@0 {
1148 reg = <0x01f03400 0x400>;
1154 pinctrl-0 = <&p2wi_pins>;
1157 #size-cells = <0>;