arm/dts/sun5i.dtsi

2  * Copyright 2012-2015 Maxime Ripard
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun4i-a10-pll2.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 	interrupt-parent = <&intc>;
55 		#address-cells = <1>;
56 		#size-cells = <0>;
60 			compatible = "arm,cortex-a8";
67 		#address-cells = <1>;
68 		#size-cells = <1>;
72 		 * This is a dummy clock, to be used as placeholder on
73 		 * other mux clocks when a specific parent clock is not
78 			#clock-cells = <0>;
79 			compatible = "fixed-clock";
80 			clock-frequency = <0>;
84 			#clock-cells = <0>;
85 			compatible = "allwinner,sun4i-a10-osc-clk";
87 			clock-frequency = <24000000>;
88 			clock-output-names = "osc24M";
92 			compatible = "fixed-factor-clock";
93 			#clock-cells = <0>;
94 			clock-div = <8>;
95 			clock-mult = <1>;
97 			clock-output-names = "osc3M";
101 			#clock-cells = <0>;
102 			compatible = "fixed-clock";
103 			clock-frequency = <32768>;
104 			clock-output-names = "osc32k";
108 			#clock-cells = <0>;
109 			compatible = "allwinner,sun4i-a10-pll1-clk";
112 			clock-output-names = "pll1";
116 			#clock-cells = <1>;
117 			compatible = "allwinner,sun5i-a13-pll2-clk";
120 			clock-output-names = "pll2-1x", "pll2-2x",
121 					     "pll2-4x", "pll2-8x";
125 			#clock-cells = <0>;
126 			compatible = "allwinner,sun4i-a10-pll3-clk";
129 			clock-output-names = "pll3";
133 			compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
134 			#clock-cells = <0>;
135 			clock-div = <1>;
136 			clock-mult = <2>;
138 			clock-output-names = "pll3-2x";
142 			#clock-cells = <0>;
143 			compatible = "allwinner,sun4i-a10-pll1-clk";
146 			clock-output-names = "pll4";
150 			#clock-cells = <1>;
151 			compatible = "allwinner,sun4i-a10-pll5-clk";
154 			clock-output-names = "pll5_ddr", "pll5_other";
158 			#clock-cells = <1>;
159 			compatible = "allwinner,sun4i-a10-pll6-clk";
162 			clock-output-names = "pll6_sata", "pll6_other", "pll6";
166 			#clock-cells = <0>;
167 			compatible = "allwinner,sun4i-a10-pll3-clk";
170 			clock-output-names = "pll7";
174 			compatible = "fixed-factor-clock";
175 			#clock-cells = <0>;
176 			clock-div = <1>;
177 			clock-mult = <2>;
179 			clock-output-names = "pll7-2x";
184 			#clock-cells = <0>;
185 			compatible = "allwinner,sun4i-a10-cpu-clk";
188 			clock-output-names = "cpu";
192 			#clock-cells = <0>;
193 			compatible = "allwinner,sun4i-a10-axi-clk";
196 			clock-output-names = "axi";
200 			#clock-cells = <0>;
201 			compatible = "allwinner,sun5i-a13-ahb-clk";
204 			clock-output-names = "ahb";
209 			assigned-clocks = <&ahb>;
210 			assigned-clock-parents = <&pll6 1>;
214 			#clock-cells = <0>;
215 			compatible = "allwinner,sun4i-a10-apb0-clk";
218 			clock-output-names = "apb0";
222 			#clock-cells = <0>;
223 			compatible = "allwinner,sun4i-a10-apb1-clk";
226 			clock-output-names = "apb1";
230 			#clock-cells = <1>;
231 			compatible = "allwinner,sun4i-a10-axi-gates-clk";
234 			clock-indices = <0>;
235 			clock-output-names = "axi_dram";
239 			#clock-cells = <0>;
240 			compatible = "allwinner,sun4i-a10-mod0-clk";
243 			clock-output-names = "nand";
247 			#clock-cells = <0>;
248 			compatible = "allwinner,sun4i-a10-mod0-clk";
251 			clock-output-names = "ms";
255 			#clock-cells = <1>;
256 			compatible = "allwinner,sun4i-a10-mmc-clk";
259 			clock-output-names = "mmc0",
265 			#clock-cells = <1>;
266 			compatible = "allwinner,sun4i-a10-mmc-clk";
269 			clock-output-names = "mmc1",
275 			#clock-cells = <1>;
276 			compatible = "allwinner,sun4i-a10-mmc-clk";
279 			clock-output-names = "mmc2",
285 			#clock-cells = <0>;
286 			compatible = "allwinner,sun4i-a10-mod0-clk";
289 			clock-output-names = "ts";
293 			#clock-cells = <0>;
294 			compatible = "allwinner,sun4i-a10-mod0-clk";
297 			clock-output-names = "ss";
301 			#clock-cells = <0>;
302 			compatible = "allwinner,sun4i-a10-mod0-clk";
305 			clock-output-names = "spi0";
309 			#clock-cells = <0>;
310 			compatible = "allwinner,sun4i-a10-mod0-clk";
313 			clock-output-names = "spi1";
317 			#clock-cells = <0>;
318 			compatible = "allwinner,sun4i-a10-mod0-clk";
321 			clock-output-names = "spi2";
325 			#clock-cells = <0>;
326 			compatible = "allwinner,sun4i-a10-mod0-clk";
329 			clock-output-names = "ir0";
333 			#clock-cells = <1>;
334 			#reset-cells = <1>;
335 			compatible = "allwinner,sun5i-a13-usb-clk";
338 			clock-output-names = "usb_ohci0", "usb_phy";
342 			#clock-cells = <0>;
343 			compatible = "allwinner,sun4i-a10-codec-clk";
346 			clock-output-names = "codec";
350 			#clock-cells = <0>;
351 			compatible = "allwinner,sun5i-a13-mbus-clk";
354 			clock-output-names = "mbus";
359 		compatible = "simple-bus";
360 		#address-cells = <1>;
361 		#size-cells = <1>;
364 		sram-controller@01c00000 {
365 			compatible = "allwinner,sun4i-a10-sram-controller";
367 			#address-cells = <1>;
368 			#size-cells = <1>;
372 				compatible = "mmio-sram";
374 				#address-cells = <1>;
375 				#size-cells = <1>;
380 				compatible = "mmio-sram";
382 				#address-cells = <1>;
383 				#size-cells = <1>;
386 				otg_sram: sram-section@0000 {
387 					compatible = "allwinner,sun4i-a10-sram-d";
394 		dma: dma-controller@01c02000 {
395 			compatible = "allwinner,sun4i-a10-dma";
399 			#dma-cells = <2>;
403 			compatible = "allwinner,sun4i-a10-spi";
407 			clock-names = "ahb", "mod";
410 			dma-names = "rx", "tx";
412 			#address-cells = <1>;
413 			#size-cells = <0>;
417 			compatible = "allwinner,sun4i-a10-spi";
421 			clock-names = "ahb", "mod";
424 			dma-names = "rx", "tx";
426 			#address-cells = <1>;
427 			#size-cells = <0>;
431 			compatible = "allwinner,sun5i-a13-mmc";
437 			clock-names = "ahb",
439 				      "output",
443 			#address-cells = <1>;
444 			#size-cells = <0>;
448 			compatible = "allwinner,sun5i-a13-mmc";
454 			clock-names = "ahb",
456 				      "output",
460 			#address-cells = <1>;
461 			#size-cells = <0>;
465 			compatible = "allwinner,sun5i-a13-mmc";
471 			clock-names = "ahb",
473 				      "output",
477 			#address-cells = <1>;
478 			#size-cells = <0>;
482 			compatible = "allwinner,sun4i-a10-musb";
486 			interrupt-names = "mc";
488 			phy-names = "usb";
495 			#phy-cells = <1>;
496 			compatible = "allwinner,sun5i-a13-usb-phy";
498 			reg-names = "phy_ctrl", "pmu1";
500 			clock-names = "usb_phy";
502 			reset-names = "usb0_reset", "usb1_reset";
507 			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
512 			phy-names = "usb";
517 			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
522 			phy-names = "usb";
527 			compatible = "allwinner,sun4i-a10-spi";
531 			clock-names = "ahb", "mod";
534 			dma-names = "rx", "tx";
536 			#address-cells = <1>;
537 			#size-cells = <0>;
540 		intc: interrupt-controller@01c20400 {
541 			compatible = "allwinner,sun4i-a10-ic";
543 			interrupt-controller;
544 			#interrupt-cells = <1>;
551 			gpio-controller;
552 			interrupt-controller;
553 			#interrupt-cells = <3>;
554 			#gpio-cells = <3>;
601 			uart3_pins_cts_rts_a: uart3-cts-rts@0 {
617 			compatible = "allwinner,sun4i-a10-timer";
624 			compatible = "allwinner,sun4i-a10-wdt";
629 			compatible = "allwinner,sun4i-a10-lradc-keys";
636 			#sound-dai-cells = <0>;
637 			compatible = "allwinner,sun4i-a10-codec";
641 			clock-names = "apb", "codec";
644 			dma-names = "rx", "tx";
649 			compatible = "allwinner,sun4i-a10-sid";
654 			compatible = "allwinner,sun5i-a13-ts";
657 			#thermal-sensor-cells = <0>;
661 			compatible = "snps,dw-apb-uart";
664 			reg-shift = <2>;
665 			reg-io-width = <4>;
671 			compatible = "snps,dw-apb-uart";
674 			reg-shift = <2>;
675 			reg-io-width = <4>;
681 			compatible = "allwinner,sun4i-a10-i2c";
686 			#address-cells = <1>;
687 			#size-cells = <0>;
691 			compatible = "allwinner,sun4i-a10-i2c";
696 			#address-cells = <1>;
697 			#size-cells = <0>;
701 			compatible = "allwinner,sun4i-a10-i2c";
706 			#address-cells = <1>;
707 			#size-cells = <0>;
711 			compatible = "allwinner,sun5i-a13-hstimer";