arm/dts/sun5i.dtsi

55 		#address-cells = <1>;
67 		#address-cells = <1>;
68 		#size-cells = <1>;
95 			clock-mult = <1>;
116 			#clock-cells = <1>;
120 			clock-output-names = "pll2-1x", "pll2-2x",
135 			clock-div = <1>;
150 			#clock-cells = <1>;
158 			#clock-cells = <1>;
176 			clock-div = <1>;
203 			clocks = <&axi>, <&cpu>, <&pll6 1>;
210 			assigned-clock-parents = <&pll6 1>;
225 			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
230 			#clock-cells = <1>;
242 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 			#clock-cells = <1>;
258 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
265 			#clock-cells = <1>;
268 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 			#clock-cells = <1>;
278 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
304 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
312 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
328 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
333 			#clock-cells = <1>;
334 			#reset-cells = <1>;
337 			clocks = <&pll6 1>;
353 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
360 		#address-cells = <1>;
361 		#size-cells = <1>;
367 			#address-cells = <1>;
368 			#size-cells = <1>;
374 				#address-cells = <1>;
375 				#size-cells = <1>;
382 				#address-cells = <1>;
383 				#size-cells = <1>;
412 			#address-cells = <1>;
426 			#address-cells = <1>;
435 				 <&mmc0_clk 1>,
443 			#address-cells = <1>;
452 				 <&mmc1_clk 1>,
460 			#address-cells = <1>;
469 				 <&mmc2_clk 1>,
477 			#address-cells = <1>;
490 			allwinner,sram = <&otg_sram 1>;
495 			#phy-cells = <1>;
501 			resets = <&usb_clk 0>, <&usb_clk 1>;
510 			clocks = <&ahb_gates 1>;
511 			phys = <&usbphy 1>;
521 			phys = <&usbphy 1>;
536 			#address-cells = <1>;
544 			#interrupt-cells = <1>;
616 		timer@01c20c00 {
686 			#address-cells = <1>;
694 			clocks = <&apb1_gates 1>;
696 			#address-cells = <1>;
706 			#address-cells = <1>;