arm/dts/sun5i.dtsi

56 		#size-cells = <0>;
58 		cpu0: cpu@0 {
61 			reg = <0x0>;
78 			#clock-cells = <0>;
80 			clock-frequency = <0>;
84 			#clock-cells = <0>;
86 			reg = <0x01c20050 0x4>;
93 			#clock-cells = <0>;
100 		osc32k: clk@0 {
101 			#clock-cells = <0>;
108 			#clock-cells = <0>;
110 			reg = <0x01c20000 0x4>;
118 			reg = <0x01c20008 0x8>;
125 			#clock-cells = <0>;
127 			reg = <0x01c20010 0x4>;
134 			#clock-cells = <0>;
142 			#clock-cells = <0>;
144 			reg = <0x01c20018 0x4>;
152 			reg = <0x01c20020 0x4>;
160 			reg = <0x01c20028 0x4>;
166 			#clock-cells = <0>;
168 			reg = <0x01c20030 0x4>;
175 			#clock-cells = <0>;
184 			#clock-cells = <0>;
186 			reg = <0x01c20054 0x4>;
192 			#clock-cells = <0>;
194 			reg = <0x01c20054 0x4>;
200 			#clock-cells = <0>;
202 			reg = <0x01c20054 0x4>;
214 			#clock-cells = <0>;
216 			reg = <0x01c20054 0x4>;
222 			#clock-cells = <0>;
224 			reg = <0x01c20058 0x4>;
232 			reg = <0x01c2005c 0x4>;
234 			clock-indices = <0>;
239 			#clock-cells = <0>;
241 			reg = <0x01c20080 0x4>;
247 			#clock-cells = <0>;
249 			reg = <0x01c20084 0x4>;
257 			reg = <0x01c20088 0x4>;
267 			reg = <0x01c2008c 0x4>;
277 			reg = <0x01c20090 0x4>;
285 			#clock-cells = <0>;
287 			reg = <0x01c20098 0x4>;
293 			#clock-cells = <0>;
295 			reg = <0x01c2009c 0x4>;
301 			#clock-cells = <0>;
303 			reg = <0x01c200a0 0x4>;
309 			#clock-cells = <0>;
311 			reg = <0x01c200a4 0x4>;
317 			#clock-cells = <0>;
319 			reg = <0x01c200a8 0x4>;
325 			#clock-cells = <0>;
327 			reg = <0x01c200b0 0x4>;
336 			reg = <0x01c200cc 0x4>;
342 			#clock-cells = <0>;
344 			reg = <0x01c20140 0x4>;
350 			#clock-cells = <0>;
352 			reg = <0x01c2015c 0x4>;
366 			reg = <0x01c00000 0x30>;
373 				reg = <0x00000000 0xc000>;
376 				ranges = <0 0x00000000 0xc000>;
381 				reg = <0x00010000 0x1000>;
384 				ranges = <0 0x00010000 0x1000>;
388 					reg = <0x0000 0x1000>;
396 			reg = <0x01c02000 0x1000>;
404 			reg = <0x01c05000 0x1000>;
413 			#size-cells = <0>;
418 			reg = <0x01c06000 0x1000>;
427 			#size-cells = <0>;
432 			reg = <0x01c0f000 0x1000>;
434 				 <&mmc0_clk 0>,
444 			#size-cells = <0>;
449 			reg = <0x01c10000 0x1000>;
451 				 <&mmc1_clk 0>,
461 			#size-cells = <0>;
466 			reg = <0x01c11000 0x1000>;
468 				 <&mmc2_clk 0>,
478 			#size-cells = <0>;
483 			reg = <0x01c13000 0x0400>;
484 			clocks = <&ahb_gates 0>;
487 			phys = <&usbphy 0>;
489 			extcon = <&usbphy 0>;
497 			reg = <0x01c13400 0x10 0x01c14800 0x4>;
501 			resets = <&usb_clk 0>, <&usb_clk 1>;
508 			reg = <0x01c14000 0x100>;
518 			reg = <0x01c14400 0x100>;
528 			reg = <0x01c17000 0x1000>;
537 			#size-cells = <0>;
542 			reg = <0x01c20400 0x400>;
548 			reg = <0x01c20800 0x400>;
556 			i2c0_pins_a: i2c0@0 {
563 			i2c1_pins_a: i2c1@0 {
570 			i2c2_pins_a: i2c2@0 {
577 			mmc0_pins_a: mmc0@0 {
585 			mmc2_pins_a: mmc2@0 {
594 			uart3_pins_a: uart3@0 {
601 			uart3_pins_cts_rts_a: uart3-cts-rts@0 {
618 			reg = <0x01c20c00 0x90>;
625 			reg = <0x01c20c90 0x10>;
630 			reg = <0x01c22800 0x100>;
636 			#sound-dai-cells = <0>;
638 			reg = <0x01c22c00 0x40>;
640 			clocks = <&apb0_gates 0>, <&codec_clk>;
650 			reg = <0x01c23800 0x10>;
655 			reg = <0x01c25000 0x100>;
657 			#thermal-sensor-cells = <0>;
662 			reg = <0x01c28400 0x400>;
672 			reg = <0x01c28c00 0x400>;
682 			reg = <0x01c2ac00 0x400>;
684 			clocks = <&apb1_gates 0>;
687 			#size-cells = <0>;
692 			reg = <0x01c2b000 0x400>;
697 			#size-cells = <0>;
702 			reg = <0x01c2b400 0x400>;
707 			#size-cells = <0>;
712 			reg = <0x01c60000 0x1000>;