arm/dts/sun5i-gr8.dtsi

51 	#address-cells = <1>;
52 	#size-cells = <1>;
55 		#address-cells = <1>;
67 		#address-cells = <1>;
68 		#size-cells = <1>;
95 			clock-mult = <1>;
116 			#clock-cells = <1>;
120 			clock-output-names = "pll2-1x", "pll2-2x",
135 			clock-div = <1>;
150 			#clock-cells = <1>;
158 			#clock-cells = <1>;
176 			clock-div = <1>;
203 			clocks = <&axi>, <&cpu>, <&pll6 1>;
210 			assigned-clock-parents = <&pll6 1>;
225 			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
230 			#clock-cells = <1>;
239 			#clock-cells = <1>;
243 			clock-indices = <0>, <1>,
266 			#clock-cells = <1>;
277 			#clock-cells = <1>;
281 			clock-indices = <0>, <1>,
293 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
301 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
306 			#clock-cells = <1>;
309 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
316 			#clock-cells = <1>;
319 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
326 			#clock-cells = <1>;
329 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
339 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
347 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
355 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
363 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
371 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
379 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
406 			#clock-cells = <1>;
407 			#reset-cells = <1>;
410 			clocks = <&pll6 1>;
415 			#clock-cells = <1>;
421 					<1>,
439 			clocks = <&pll3>, <&pll7>, <&pll5 1>;
448 			clocks = <&pll3>, <&pll7>, <&pll5 1>;
454 			#reset-cells = <1>;
481 			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
493 		#address-cells = <1>;
494 		#size-cells = <1>;
500 			#address-cells = <1>;
501 			#size-cells = <1>;
507 				#address-cells = <1>;
508 				#size-cells = <1>;
515 				#address-cells = <1>;
516 				#size-cells = <1>;
544 			#address-cells = <1>;
558 			#address-cells = <1>;
572 			#address-cells = <1>;
584 				#address-cells = <1>;
598 			resets = <&tcon_ch0_clk 1>;
610 				#address-cells = <1>;
614 					#address-cells = <1>;
624 				tcon0_out: port@1 {
625 					#address-cells = <1>;
627 					reg = <1>;
629 					tcon0_out_tve0: endpoint@1 {
630 						reg = <1>;
642 				 <&mmc0_clk 1>,
650 			#address-cells = <1>;
659 				 <&mmc1_clk 1>,
667 			#address-cells = <1>;
676 				 <&mmc2_clk 1>,
684 			#address-cells = <1>;
697 			allwinner,sram = <&otg_sram 1>;
704 			#phy-cells = <1>;
710 			resets = <&usb_clk 0>, <&usb_clk 1>;
719 			clocks = <&ahb_gates 1>;
720 			phys = <&usbphy 1>;
730 			phys = <&usbphy 1>;
745 			#address-cells = <1>;
753 			#interrupt-cells = <1>;
871 			uart1_pins_a: uart1@1 {
885 			uart2_pins_a: uart2@1 {
899 			uart3_pins_a: uart3@1 {
922 		timer@01c20c00 {
939 			clocks = <&apb0_gates 1>, <&spdif_clk>;
1032 			#address-cells = <1>;
1040 			clocks = <&apb1_gates 1>;
1042 			#address-cells = <1>;
1052 			#address-cells = <1>;
1075 				#address-cells = <1>;
1078 				fe0_out: port@1 {
1079 					#address-cells = <1>;
1081 					reg = <1>;
1105 				#address-cells = <1>;
1109 					#address-cells = <1>;
1119 				be0_out: port@1 {
1120 					#address-cells = <1>;
1122 					reg = <1>;