Lines Matching +full:0 +full:x01c2005c
56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0x0>;
78 #clock-cells = <0>;
80 clock-frequency = <0>;
84 #clock-cells = <0>;
86 reg = <0x01c20050 0x4>;
93 #clock-cells = <0>;
100 osc32k: clk@0 {
101 #clock-cells = <0>;
108 #clock-cells = <0>;
110 reg = <0x01c20000 0x4>;
118 reg = <0x01c20008 0x8>;
125 #clock-cells = <0>;
127 reg = <0x01c20010 0x4>;
134 #clock-cells = <0>;
142 #clock-cells = <0>;
144 reg = <0x01c20018 0x4>;
152 reg = <0x01c20020 0x4>;
160 reg = <0x01c20028 0x4>;
166 #clock-cells = <0>;
168 reg = <0x01c20030 0x4>;
175 #clock-cells = <0>;
184 #clock-cells = <0>;
186 reg = <0x01c20054 0x4>;
192 #clock-cells = <0>;
194 reg = <0x01c20054 0x4>;
200 #clock-cells = <0>;
202 reg = <0x01c20054 0x4>;
214 #clock-cells = <0>;
216 reg = <0x01c20054 0x4>;
222 #clock-cells = <0>;
224 reg = <0x01c20058 0x4>;
232 reg = <0x01c2005c 0x4>;
234 clock-indices = <0>;
241 reg = <0x01c20060 0x8>;
243 clock-indices = <0>, <1>,
268 reg = <0x01c20068 0x4>;
270 clock-indices = <0>, <3>,
279 reg = <0x01c2006c 0x4>;
281 clock-indices = <0>, <1>,
290 #clock-cells = <0>;
292 reg = <0x01c20080 0x4>;
298 #clock-cells = <0>;
300 reg = <0x01c20084 0x4>;
308 reg = <0x01c20088 0x4>;
318 reg = <0x01c2008c 0x4>;
328 reg = <0x01c20090 0x4>;
336 #clock-cells = <0>;
338 reg = <0x01c20098 0x4>;
344 #clock-cells = <0>;
346 reg = <0x01c2009c 0x4>;
352 #clock-cells = <0>;
354 reg = <0x01c200a0 0x4>;
360 #clock-cells = <0>;
362 reg = <0x01c200a4 0x4>;
368 #clock-cells = <0>;
370 reg = <0x01c200a8 0x4>;
376 #clock-cells = <0>;
378 reg = <0x01c200b0 0x4>;
384 #clock-cells = <0>;
386 reg = <0x01c200b8 0x4>;
395 #clock-cells = <0>;
397 reg = <0x01c200c0 0x4>;
409 reg = <0x01c200cc 0x4>;
418 reg = <0x01c20100 0x4>;
419 clocks = <&pll5 0>;
420 clock-indices = <0>,
435 #clock-cells = <0>;
436 #reset-cells = <0>;
438 reg = <0x01c20104 0x4>;
444 #clock-cells = <0>;
445 #reset-cells = <0>;
447 reg = <0x01c2010c 0x4>;
453 #clock-cells = <0>;
456 reg = <0x01c20118 0x4>;
462 #clock-cells = <0>;
464 reg = <0x01c2012c 0x4>;
470 #clock-cells = <0>;
472 reg = <0x01c20140 0x4>;
478 #clock-cells = <0>;
480 reg = <0x01c2015c 0x4>;
499 reg = <0x01c00000 0x30>;
506 reg = <0x00000000 0xc000>;
509 ranges = <0 0x00000000 0xc000>;
514 reg = <0x00010000 0x1000>;
517 ranges = <0 0x00010000 0x1000>;
521 reg = <0x0000 0x1000>;
529 reg = <0x01c02000 0x1000>;
537 reg = <0x01c03000 0x1000>;
545 #size-cells = <0>;
550 reg = <0x01c05000 0x1000>;
559 #size-cells = <0>;
564 reg = <0x01c06000 0x1000>;
573 #size-cells = <0>;
578 reg = <0x01c0a000 0x1000>;
580 resets = <&tcon_ch0_clk 0>;
585 #size-cells = <0>;
587 tve0_in_tcon0: endpoint@0 {
588 reg = <0>;
596 reg = <0x01c0c000 0x1000>;
611 #size-cells = <0>;
613 tcon0_in: port@0 {
615 #size-cells = <0>;
616 reg = <0>;
618 tcon0_in_be0: endpoint@0 {
619 reg = <0>;
626 #size-cells = <0>;
639 reg = <0x01c0f000 0x1000>;
641 <&mmc0_clk 0>,
651 #size-cells = <0>;
656 reg = <0x01c10000 0x1000>;
658 <&mmc1_clk 0>,
668 #size-cells = <0>;
673 reg = <0x01c11000 0x1000>;
675 <&mmc2_clk 0>,
685 #size-cells = <0>;
690 reg = <0x01c13000 0x0400>;
691 clocks = <&ahb_gates 0>;
694 phys = <&usbphy 0>;
696 extcon = <&usbphy 0>;
706 reg = <0x01c13400 0x10 0x01c14800 0x4>;
710 resets = <&usb_clk 0>, <&usb_clk 1>;
717 reg = <0x01c14000 0x100>;
727 reg = <0x01c14400 0x100>;
737 reg = <0x01c17000 0x1000>;
746 #size-cells = <0>;
751 reg = <0x01c20400 0x400>;
758 reg = <0x01c20800 0x400>;
766 i2c0_pins_a: i2c0@0 {
773 i2c1_pins_a: i2c1@0 {
780 i2c2_pins_a: i2c2@0 {
787 i2s0_data_pins_a: i2s0-data@0 {
794 i2s0_mclk_pins_a: i2s0-mclk@0 {
801 ir0_rx_pins_a: ir0@0 {
808 lcd_rgb666_pins: lcd-rgb666@0 {
818 mmc0_pins_a: mmc0@0 {
826 nand_pins_a: nand-base0@0 {
836 nand_cs0_pins_a: nand-cs@0 {
843 nand_rb0_pins_a: nand-rb@0 {
850 pwm0_pins_a: pwm0@0 {
864 spdif_tx_pins_a: spdif@0 {
878 uart1_cts_rts_pins_a: uart1-cts-rts@0 {
892 uart2_cts_rts_pins_a: uart2-cts-rts@0 {
906 uart3_cts_rts_pins_a: uart3-cts-rts@0 {
916 reg = <0x01c20e00 0xc>;
924 reg = <0x01c20c00 0x90>;
931 reg = <0x01c20c90 0x10>;
935 #sound-dai-cells = <0>;
937 reg = <0x01c21000 0x400>;
952 reg = <0x01c21800 0x40>;
957 #sound-dai-cells = <0>;
959 reg = <0x01c22400 0x400>;
971 reg = <0x01c22800 0x100>;
977 #sound-dai-cells = <0>;
979 reg = <0x01c22c00 0x40>;
981 clocks = <&apb0_gates 0>, <&codec_clk>;
991 reg = <0x01c25000 0x100>;
993 #thermal-sensor-cells = <0>;
998 reg = <0x01c28400 0x400>;
1008 reg = <0x01c28800 0x400>;
1018 reg = <0x01c28c00 0x400>;
1028 reg = <0x01c2ac00 0x400>;
1030 clocks = <&apb1_gates 0>;
1033 #size-cells = <0>;
1038 reg = <0x01c2b000 0x400>;
1043 #size-cells = <0>;
1048 reg = <0x01c2b400 0x400>;
1053 #size-cells = <0>;
1058 reg = <0x01c60000 0x1000>;
1065 reg = <0x01e00000 0x20000>;
1076 #size-cells = <0>;
1080 #size-cells = <0>;
1083 fe0_out_be0: endpoint@0 {
1084 reg = <0>;
1093 reg = <0x01e60000 0x10000>;
1106 #size-cells = <0>;
1108 be0_in: port@0 {
1110 #size-cells = <0>;
1111 reg = <0>;
1113 be0_in_fe0: endpoint@0 {
1114 reg = <0>;
1121 #size-cells = <0>;
1124 be0_out_tcon0: endpoint@0 {
1125 reg = <0>;