arm/dts/sun5i-a13.dtsi

4  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
50 #include <dt-bindings/thermal/thermal.h>
53 	interrupt-parent = <&intc>;
56 		#address-cells = <1>;
57 		#size-cells = <1>;
61 			compatible = "allwinner,simple-framebuffer",
62 				     "simple-framebuffer";
63 			allwinner,pipeline = "de_be0-lcd0";
70 	thermal-zones {
73 			polling-delay-passive = <250>;
74 			polling-delay = <1000>;
75 			thermal-sensors = <&rtp>;
77 			cooling-maps {
80 					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
104 			#clock-cells = <1>;
105 			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
108 			clock-indices = <0>, <1>,
118 			clock-output-names = "ahb_usbotg", "ahb_ehci",
131 			#clock-cells = <1>;
132 			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
135 			clock-indices = <0>, <5>,
137 			clock-output-names = "apb0_codec", "apb0_pio",
142 			#clock-cells = <1>;
143 			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
146 			clock-indices = <0>, <1>,
149 			clock-output-names = "apb1_i2c0", "apb1_i2c1",
155 			#clock-cells = <1>;
156 			compatible = "allwinner,sun5i-a13-dram-gates-clk",
157 				     "allwinner,sun4i-a10-gates-clk";
160 			clock-indices = <0>,
166 			clock-output-names = "dram_ve",
175 			#clock-cells = <0>;
176 			#reset-cells = <0>;
177 			compatible = "allwinner,sun4i-a10-display-clk";
180 			clock-output-names = "de-be";
184 			#clock-cells = <0>;
185 			#reset-cells = <0>;
186 			compatible = "allwinner,sun4i-a10-display-clk";
189 			clock-output-names = "de-fe";
193 			#clock-cells = <0>;
194 			#reset-cells = <1>;
195 			compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
198 			clock-output-names = "tcon-ch0-sclk";
202 			#clock-cells = <0>;
203 			compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
206 			clock-output-names = "tcon-ch1-sclk";
210 	display-engine {
211 		compatible = "allwinner,sun5i-a13-display-engine";
216 		tcon0: lcd-controller@01c0c000 {
217 			compatible = "allwinner,sun5i-a13-tcon";
221 			reset-names = "lcd";
225 			clock-names = "ahb",
226 				      "tcon-ch0",
227 				      "tcon-ch1";
228 			clock-output-names = "tcon-pixel-clock";
232 				#address-cells = <1>;
233 				#size-cells = <0>;
236 					#address-cells = <1>;
237 					#size-cells = <0>;
242 						remote-endpoint = <&be0_out_tcon0>;
247 					#address-cells = <1>;
248 					#size-cells = <0>;
255 			compatible = "allwinner,sun5i-a13-pwm";
258 			#pwm-cells = <3>;
262 		fe0: display-frontend@01e00000 {
263 			compatible = "allwinner,sun5i-a13-display-frontend";
268 			clock-names = "ahb", "mod",
274 				#address-cells = <1>;
275 				#size-cells = <0>;
278 					#address-cells = <1>;
279 					#size-cells = <0>;
284 						remote-endpoint = <&be0_in_fe0>;
290 		be0: display-backend@01e60000 {
291 			compatible = "allwinner,sun5i-a13-display-backend";
295 			clock-names = "ahb", "mod",
300 			assigned-clocks = <&de_be_clk>;
301 			assigned-clock-rates = <300000000>;
304 				#address-cells = <1>;
305 				#size-cells = <0>;
308 					#address-cells = <1>;
309 					#size-cells = <0>;
314 						remote-endpoint = <&fe0_out_be0>;
319 					#address-cells = <1>;
320 					#size-cells = <0>;
325 						remote-endpoint = <&tcon0_in_be0>;
334 	clock-latency = <244144>; /* 8 32k periods */
335 	operating-points = <
344 	#cooling-cells = <2>;
345 	cooling-min-level = <0>;
346 	cooling-max-level = <5>;
350 	compatible = "allwinner,sun5i-a13-pinctrl";