Lines Matching +full:1 +full:c2012c
56 #address-cells = <1>;
57 #size-cells = <1>;
104 #clock-cells = <1>;
108 clock-indices = <0>, <1>,
131 #clock-cells = <1>;
142 #clock-cells = <1>;
146 clock-indices = <0>, <1>,
155 #clock-cells = <1>;
161 <1>,
179 clocks = <&pll3>, <&pll7>, <&pll5 1>;
188 clocks = <&pll3>, <&pll7>, <&pll5 1>;
194 #reset-cells = <1>;
201 tcon_ch1_clk: clk@01c2012c {
220 resets = <&tcon_ch0_clk 1>;
232 #address-cells = <1>;
236 #address-cells = <1>;
246 tcon0_out: port@1 {
247 #address-cells = <1>;
249 reg = <1>;
274 #address-cells = <1>;
277 fe0_out: port@1 {
278 #address-cells = <1>;
280 reg = <1>;
304 #address-cells = <1>;
308 #address-cells = <1>;
318 be0_out: port@1 {
319 #address-cells = <1>;
321 reg = <1>;
369 uart1_pins_b: uart1@1 {