Lines Matching +full:0 +full:x01c20c00
64 framebuffer@0 {
110 #size-cells = <0>;
111 cpu0: cpu@0 {
114 reg = <0x0>;
125 cooling-min-level = <0>;
163 reg = <0x40000000 0x80000000>;
178 #clock-cells = <0>;
180 clock-frequency = <0>;
184 #clock-cells = <0>;
186 reg = <0x01c20050 0x4>;
193 #clock-cells = <0>;
200 osc32k: clk@0 {
201 #clock-cells = <0>;
208 #clock-cells = <0>;
210 reg = <0x01c20000 0x4>;
218 reg = <0x01c20008 0x8>;
225 #clock-cells = <0>;
227 reg = <0x01c20010 0x4>;
234 #clock-cells = <0>;
242 #clock-cells = <0>;
244 reg = <0x01c20018 0x4>;
252 reg = <0x01c20020 0x4>;
260 reg = <0x01c20028 0x4>;
266 #clock-cells = <0>;
268 reg = <0x01c20030 0x4>;
275 #clock-cells = <0>;
284 #clock-cells = <0>;
286 reg = <0x01c20054 0x4>;
292 #clock-cells = <0>;
294 reg = <0x01c20054 0x4>;
302 reg = <0x01c2005c 0x4>;
304 clock-indices = <0>;
309 #clock-cells = <0>;
311 reg = <0x01c20054 0x4>;
319 reg = <0x01c20060 0x8>;
321 clock-indices = <0>, <1>,
354 #clock-cells = <0>;
356 reg = <0x01c20054 0x4>;
364 reg = <0x01c20068 0x4>;
366 clock-indices = <0>, <1>,
377 #clock-cells = <0>;
379 reg = <0x01c20058 0x4>;
387 reg = <0x01c2006c 0x4>;
389 clock-indices = <0>, <1>,
408 #clock-cells = <0>;
410 reg = <0x01c20080 0x4>;
416 #clock-cells = <0>;
418 reg = <0x01c20084 0x4>;
426 reg = <0x01c20088 0x4>;
436 reg = <0x01c2008c 0x4>;
446 reg = <0x01c20090 0x4>;
456 reg = <0x01c20094 0x4>;
464 #clock-cells = <0>;
466 reg = <0x01c20098 0x4>;
472 #clock-cells = <0>;
474 reg = <0x01c2009c 0x4>;
480 #clock-cells = <0>;
482 reg = <0x01c200a0 0x4>;
488 #clock-cells = <0>;
490 reg = <0x01c200a4 0x4>;
496 #clock-cells = <0>;
498 reg = <0x01c200a8 0x4>;
504 #clock-cells = <0>;
506 reg = <0x01c200ac 0x4>;
512 #clock-cells = <0>;
514 reg = <0x01c200b0 0x4>;
520 #clock-cells = <0>;
522 reg = <0x01c200b4 0x4>;
528 #clock-cells = <0>;
530 reg = <0x01c200c0 0x4>;
542 reg = <0x01c200cc 0x4>;
549 #clock-cells = <0>;
551 reg = <0x01c200d4 0x4>;
559 reg = <0x01c20100 0x4>;
560 clocks = <&pll5 0>;
561 clock-indices = <0>,
582 #clock-cells = <0>;
583 #reset-cells = <0>;
585 reg = <0x01c20104 0x4>;
591 #clock-cells = <0>;
592 #reset-cells = <0>;
594 reg = <0x01c20108 0x4>;
600 #clock-cells = <0>;
601 #reset-cells = <0>;
603 reg = <0x01c2010c 0x4>;
609 #clock-cells = <0>;
610 #reset-cells = <0>;
612 reg = <0x01c20110 0x4>;
619 #clock-cells = <0>;
622 reg = <0x01c20118 0x4>;
629 #clock-cells = <0>;
632 reg = <0x01c2011c 0x4>;
639 #clock-cells = <0>;
641 reg = <0x01c2012c 0x4>;
648 #clock-cells = <0>;
650 reg = <0x01c20130 0x4>;
657 #clock-cells = <0>;
658 #reset-cells = <0>;
660 reg = <0x01c2013c 0x4>;
666 #clock-cells = <0>;
668 reg = <0x01c20140 0x4>;
682 reg = <0x01c00000 0x30>;
689 reg = <0x00000000 0xc000>;
692 ranges = <0 0x00000000 0xc000>;
696 reg = <0x8000 0x4000>;
703 reg = <0x00010000 0x1000>;
706 ranges = <0 0x00010000 0x1000>;
710 reg = <0x0000 0x1000>;
718 reg = <0x01c02000 0x1000>;
726 reg = <0x01c03000 0x1000>;
734 #size-cells = <0>;
739 reg = <0x01c05000 0x1000>;
748 #size-cells = <0>;
753 reg = <0x01c06000 0x1000>;
762 #size-cells = <0>;
767 reg = <0x01c0b000 0x1000>;
776 reg = <0x01c0b080 0x14>;
779 #size-cells = <0>;
784 reg = <0x01c0f000 0x1000>;
786 <&mmc0_clk 0>,
796 #size-cells = <0>;
801 reg = <0x01c10000 0x1000>;
803 <&mmc1_clk 0>,
813 #size-cells = <0>;
818 reg = <0x01c11000 0x1000>;
820 <&mmc2_clk 0>,
830 #size-cells = <0>;
835 reg = <0x01c12000 0x1000>;
837 <&mmc3_clk 0>,
847 #size-cells = <0>;
852 reg = <0x01c13000 0x0400>;
853 clocks = <&ahb_gates 0>;
856 phys = <&usbphy 0>;
858 extcon = <&usbphy 0>;
866 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
870 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
877 reg = <0x01c14000 0x100>;
887 reg = <0x01c14400 0x100>;
897 reg = <0x01c15000 0x1000>;
905 reg = <0x01c17000 0x1000>;
914 #size-cells = <0>;
919 reg = <0x01c18000 0x1000>;
921 clocks = <&pll6 0>, <&ahb_gates 25>;
927 reg = <0x01c1c000 0x100>;
937 reg = <0x01c1c400 0x100>;
947 reg = <0x01c1f000 0x1000>;
956 #size-cells = <0>;
961 reg = <0x01c20400 0x400>;
968 reg = <0x01c20800 0x400>;
976 emac_pins_a: emac0@0 {
987 i2c0_pins_a: i2c0@0 {
994 i2c1_pins_a: i2c1@0 {
1001 i2c2_pins_a: i2c2@0 {
1008 ir0_rx_pins_a: ir0@0 {
1022 ir1_rx_pins_a: ir1@0 {
1036 mmc0_pins_a: mmc0@0 {
1044 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1051 ps20_pins_a: ps20@0 {
1058 ps21_pins_a: ps21@0 {
1065 pwm0_pins_a: pwm0@0 {
1072 pwm1_pins_a: pwm1@0 {
1079 spdif_tx_pins_a: spdif@0 {
1086 spi0_pins_a: spi0@0 {
1093 spi0_cs0_pins_a: spi0_cs0@0 {
1100 spi1_pins_a: spi1@0 {
1107 spi1_cs0_pins_a: spi1_cs0@0 {
1114 spi2_pins_a: spi2@0 {
1128 spi2_cs0_pins_a: spi2_cs0@0 {
1142 uart0_pins_a: uart0@0 {
1156 uart1_pins_a: uart1@0 {
1166 reg = <0x01c20c00 0x90>;
1173 reg = <0x01c20c90 0x10>;
1178 reg = <0x01c20d00 0x20>;
1184 reg = <0x01c20e00 0xc>;
1191 #sound-dai-cells = <0>;
1193 reg = <0x01c21000 0x400>;
1208 reg = <0x01c21800 0x40>;
1217 reg = <0x01c21c00 0x40>;
1223 reg = <0x01c22800 0x100>;
1229 #sound-dai-cells = <0>;
1231 reg = <0x01c22c00 0x40>;
1233 clocks = <&apb0_gates 0>, <&codec_clk>;
1243 reg = <0x01c23800 0x10>;
1248 reg = <0x01c25000 0x100>;
1250 #thermal-sensor-cells = <0>;
1255 reg = <0x01c28000 0x400>;
1265 reg = <0x01c28400 0x400>;
1275 reg = <0x01c28800 0x400>;
1285 reg = <0x01c28c00 0x400>;
1295 reg = <0x01c29000 0x400>;
1305 reg = <0x01c29400 0x400>;
1315 reg = <0x01c29800 0x400>;
1325 reg = <0x01c29c00 0x400>;
1335 reg = <0x01c2ac00 0x400>;
1337 clocks = <&apb1_gates 0>;
1340 #size-cells = <0>;
1345 reg = <0x01c2b000 0x400>;
1350 #size-cells = <0>;
1355 reg = <0x01c2b400 0x400>;
1360 #size-cells = <0>;
1365 reg = <0x01c2a000 0x400>;
1373 reg = <0x01c2a400 0x400>;