Lines Matching +full:0 +full:x400
56 #clock-cells = <0>;
58 clock-frequency = <0>;
66 reg = <0x40028000 0x8000>;
78 reg = <0xA0000000 0x1000>;
79 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
86 #size-cells = <0>;
87 reg = <0xA0001000 0x1000>, <0x90000000 0x10000000>;
91 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
96 reg = <0x40011000 0x400>;
98 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
106 reg = <0x40023800 0x400>;
115 ranges = <0 0x40020000 0x3000>;
123 reg = <0x0 0x400>;
124 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
133 reg = <0x400 0x400>;
134 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
144 reg = <0x800 0x400>;
145 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
154 reg = <0xc00 0x400>;
155 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
164 reg = <0x1000 0x400>;
165 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
174 reg = <0x1400 0x400>;
175 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
184 reg = <0x1800 0x400>;
185 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
194 reg = <0x1c00 0x400>;
195 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
204 reg = <0x2000 0x400>;
205 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
214 reg = <0x2400 0x400>;
215 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
224 reg = <0x2800 0x400>;
225 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;