Lines Matching +full:1 +full:e40000
15 #address-cells = <1>;
16 #size-cells = <1>;
19 #address-cells = <1>;
20 #size-cells = <1>;
31 #address-cells = <1>;
52 cpu@1 {
55 reg = <1>;
115 #address-cells = <1>;
116 #size-cells = <1>;
129 #reset-cells = <1>;
134 #reset-cells = <1>;
139 #reset-cells = <1>;
264 #address-cells = <1>;
279 #address-cells = <1>;
294 #address-cells = <1>;
309 #address-cells = <1>;
324 #address-cells = <1>;
339 #address-cells = <1>;
356 #address-cells = <1>;
371 #address-cells = <1>;
389 #address-cells = <1>;
390 #size-cells = <1>;
402 #phy-cells = <1>;
418 #phy-cells = <1>;
432 #phy-cells = <1>;
447 #address-cells = <1>;
645 #address-cells = <1>;
646 #size-cells = <1>;
674 st,pwm-num-chan = <1>;
766 interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
804 #mbox-cells = <1>;
806 mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>;
827 fdma1: dma-controller@8e40000 {
863 #sound-dai-cells = <1>;
878 dmas = <&fdma0 2 0 1>;
889 assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
890 assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
894 dmas = <&fdma0 3 0 1>;
910 dmas = <&fdma0 4 0 1>;
926 dmas = <&fdma0 7 0 1>;
938 dmas = <&fdma0 5 0 1>;
950 dmas = <&fdma0 6 0 1>;