Lines Matching +full:clk +full:- +full:mgr
2 * Copyright Altera Corporation (C) 2014-2017. All rights reserved.
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
22 #address-cells = <1>;
23 #size-cells = <1>;
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
64 compatible = "arm,cortex-a9-gic";
65 #interrupt-cells = <3>;
66 interrupt-controller;
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "simple-bus";
76 interrupt-parent = <&intc>;
80 compatible = "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
97 #dma-cells = <1>;
98 #dma-channels = <8>;
99 #dma-requests = <32>;
101 clock-names = "apb_pclk";
106 compatible = "altr,clk-mgr";
108 reg-names = "soc_clock_manager_OCP_SLV";
111 #address-cells = <1>;
112 #size-cells = <0>;
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
135 #address-cells = <1>;
136 #size-cells = <0>;
137 #clock-cells = <0>;
138 compatible = "altr,socfpga-a10-pll-clock";
144 #clock-cells = <0>;
145 compatible = "altr,socfpga-a10-perip-clk";
147 div-reg = <0x140 0 11>;
151 #clock-cells = <0>;
152 compatible = "altr,socfpga-a10-perip-clk";
154 div-reg = <0x144 0 11>;
158 #clock-cells = <0>;
159 compatible = "altr,socfpga-a10-perip-clk";
165 #clock-cells = <0>;
166 compatible = "altr,socfpga-a10-perip-clk";
172 #clock-cells = <0>;
173 compatible = "altr,socfpga-a10-perip-clk";
179 #clock-cells = <0>;
180 compatible = "altr,socfpga-a10-perip-clk";
186 #clock-cells = <0>;
187 compatible = "altr,socfpga-a10-perip-clk";
193 #clock-cells = <0>;
194 compatible = "altr,socfpga-a10-perip-clk";
200 #clock-cells = <0>;
201 compatible = "altr,socfpga-a10-perip-clk";
207 #clock-cells = <0>;
208 compatible = "altr,socfpga-a10-perip-clk";
214 #clock-cells = <0>;
215 compatible = "altr,socfpga-a10-perip-clk";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 #clock-cells = <0>;
225 compatible = "altr,socfpga-a10-pll-clock";
231 #clock-cells = <0>;
232 compatible = "altr,socfpga-a10-perip-clk";
234 div-reg = <0x140 16 11>;
238 #clock-cells = <0>;
239 compatible = "altr,socfpga-a10-perip-clk";
241 div-reg = <0x144 16 11>;
245 #clock-cells = <0>;
246 compatible = "altr,socfpga-a10-perip-clk";
252 #clock-cells = <0>;
253 compatible = "altr,socfpga-a10-perip-clk";
259 #clock-cells = <0>;
260 compatible = "altr,socfpga-a10-perip-clk";
266 #clock-cells = <0>;
267 compatible = "altr,socfpga-a10-perip-clk";
273 #clock-cells = <0>;
274 compatible = "altr,socfpga-a10-perip-clk";
280 #clock-cells = <0>;
281 compatible = "altr,socfpga-a10-perip-clk";
287 #clock-cells = <0>;
288 compatible = "altr,socfpga-a10-perip-clk";
294 #clock-cells = <0>;
295 compatible = "altr,socfpga-a10-perip-clk";
302 #clock-cells = <0>;
303 compatible = "altr,socfpga-a10-perip-clk";
311 #clock-cells = <0>;
312 compatible = "altr,socfpga-a10-perip-clk";
320 #clock-cells = <0>;
321 compatible = "altr,socfpga-a10-perip-clk";
329 #clock-cells = <0>;
330 compatible = "altr,socfpga-a10-perip-clk";
334 fixed-divider = <4>;
339 #clock-cells = <0>;
340 compatible = "altr,socfpga-a10-perip-clk";
342 fixed-divider = <4>;
346 #clock-cells = <0>;
347 compatible = "altr,socfpga-a10-gate-clk";
349 div-reg = <0xA8 0 2>;
350 clk-gate = <0x48 1>;
354 #clock-cells = <0>;
355 compatible = "altr,socfpga-a10-gate-clk";
357 div-reg = <0xA8 8 2>;
358 clk-gate = <0x48 2>;
362 #clock-cells = <0>;
363 compatible = "altr,socfpga-a10-gate-clk";
365 div-reg = <0xA8 16 2>;
366 clk-gate = <0x48 3>;
370 #clock-cells = <0>;
371 compatible = "altr,socfpga-a10-gate-clk";
373 fixed-divider = <4>;
374 clk-gate = <0x48 0>;
378 #clock-cells = <0>;
379 compatible = "altr,socfpga-a10-gate-clk";
381 clk-gate = <0xC8 5>;
382 clk-phase = <0 135>;
386 #clock-cells = <0>;
387 compatible = "altr,socfpga-a10-gate-clk";
389 clk-gate = <0xC8 11>;
393 #clock-cells = <0>;
394 compatible = "altr,socfpga-a10-gate-clk";
396 clk-gate = <0xC8 10>;
400 #clock-cells = <0>;
401 compatible = "altr,socfpga-a10-gate-clk";
403 clk-gate = <0xC8 9>;
407 #clock-cells = <0>;
408 compatible = "altr,socfpga-a10-gate-clk";
410 clk-gate = <0xC8 8>;
414 #clock-cells = <0>;
415 compatible = "altr,socfpga-a10-gate-clk";
417 clk-gate = <0xC8 6>;
423 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
427 interrupt-names = "macirq";
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
435 clock-names = "stmmaceth";
437 reset-names = "stmmaceth";
442 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
443 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
446 interrupt-names = "macirq";
448 mac-address = [00 00 00 00 00 00];
449 snps,multicast-filter-bins = <256>;
450 snps,perfect-filter-entries = <128>;
451 tx-fifo-depth = <4096>;
452 rx-fifo-depth = <16384>;
454 clock-names = "stmmaceth";
456 reset-names = "stmmaceth";
461 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
462 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
465 interrupt-names = "macirq";
467 mac-address = [00 00 00 00 00 00];
468 snps,multicast-filter-bins = <256>;
469 snps,perfect-filter-entries = <128>;
470 tx-fifo-depth = <4096>;
471 rx-fifo-depth = <16384>;
473 clock-names = "stmmaceth";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "snps,dw-apb-gpio";
484 porta: gpio-controller@0 {
485 compatible = "snps,dw-apb-gpio-port";
486 gpio-controller;
487 #gpio-cells = <2>;
488 snps,nr-gpios = <29>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 compatible = "snps,dw-apb-gpio";
503 portb: gpio-controller@0 {
504 compatible = "snps,dw-apb-gpio-port";
505 gpio-controller;
506 #gpio-cells = <2>;
507 snps,nr-gpios = <29>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "snps,dw-apb-gpio";
522 portc: gpio-controller@0 {
523 compatible = "snps,dw-apb-gpio-port";
524 gpio-controller;
525 #gpio-cells = <2>;
526 snps,nr-gpios = <27>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
534 fpga_mgr: fpga-mgr@ffd03000 {
535 compatible = "altr,socfpga-a10-fpga-mgr";
540 reset-names = "fpgamgr";
544 #address-cells = <1>;
545 #size-cells = <0>;
546 compatible = "snps,designware-i2c";
554 #address-cells = <1>;
555 #size-cells = <0>;
556 compatible = "snps,designware-i2c";
564 #address-cells = <1>;
565 #size-cells = <0>;
566 compatible = "snps,designware-i2c";
574 #address-cells = <1>;
575 #size-cells = <0>;
576 compatible = "snps,designware-i2c";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 compatible = "snps,designware-i2c";
599 compatible = "snps,dw-apb-ssi";
600 #address-cells = <1>;
601 #size-cells = <0>;
604 num-chipselect = <4>;
605 bus-num = <0>;
606 tx-dma-channel = <&pdma 16>;
607 rx-dma-channel = <&pdma 17>;
613 compatible = "snps,dw-apb-ssi";
614 #address-cells = <1>;
615 #size-cells = <0>;
618 num-chipselect = <4>;
619 bus-num = <0>;
620 tx-dma-channel = <&pdma 20>;
621 rx-dma-channel = <&pdma 21>;
626 L2: l2-cache@fffff000 {
627 compatible = "arm,pl310-cache";
630 cache-unified;
631 cache-level = <2>;
635 #address-cells = <1>;
636 #size-cells = <0>;
637 compatible = "altr,socfpga-dw-mshc";
640 fifo-depth = <0x400>;
641 bus-width = <4>;
643 clock-names = "biu", "ciu";
648 compatible = "mmio-sram";
653 compatible = "altr,socfpga-a10-ecc-manager";
654 altr,sysmgr-syscon = <&sysmgr>;
655 #address-cells = <1>;
656 #size-cells = <1>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
664 compatible = "altr,sdram-edac-a10";
665 altr,sdr-syscon = <&sdr>;
670 l2-ecc@ffd06010 {
671 compatible = "altr,socfpga-a10-l2-ecc";
677 ocram-ecc@ff8c3000 {
678 compatible = "altr,socfpga-a10-ocram-ecc";
684 sdmmca-ecc@ff8c2c00 {
685 compatible = "altr,socfpga-sdmmc-ecc";
687 altr,ecc-parent = <&mmc>;
694 emac0-rx-ecc@ff8c0800 {
695 compatible = "altr,socfpga-eth-mac-ecc";
697 altr,ecc-parent = <&gmac0>;
702 emac0-tx-ecc@ff8c0c00 {
703 compatible = "altr,socfpga-eth-mac-ecc";
705 altr,ecc-parent = <&gmac0>;
710 dma-ecc@ff8c8000 {
711 compatible = "altr,socfpga-dma-ecc";
713 altr,ecc-parent = <&pdma>;
718 usb0-ecc@ff8c8800 {
719 compatible = "altr,socfpga-usb-ecc";
721 altr,ecc-parent = <&usb0>;
728 #address-cells = <1>;
729 #size-cells = <0>;
735 ext-decoder = <0>; /* external decoder */
736 num-chipselect = <4>;
737 fifo-depth = <128>;
738 sram-size = <512>;
739 bus-num = <2>;
744 #reset-cells = <1>;
745 compatible = "altr,rst-mgr";
747 altr,modrst-offset = <0x20>;
750 scu: snoop-control-unit@ffffc000 {
751 compatible = "arm,cortex-a9-scu";
756 compatible = "altr,sys-mgr", "syscon";
758 cpu1-start-addr = <0xffd06230>;
763 compatible = "arm,cortex-a9-twd-timer";
770 compatible = "snps,dw-apb-timer";
774 clock-names = "timer";
778 compatible = "snps,dw-apb-timer";
782 clock-names = "timer";
786 compatible = "snps,dw-apb-timer";
790 clock-names = "timer";
794 compatible = "snps,dw-apb-timer";
798 clock-names = "timer";
802 compatible = "snps,dw-apb-uart";
805 reg-shift = <2>;
806 reg-io-width = <4>;
812 compatible = "snps,dw-apb-uart";
815 reg-shift = <2>;
816 reg-io-width = <4>;
822 #phy-cells = <0>;
823 compatible = "usb-nop-xceiv";
832 clock-names = "otg";
834 reset-names = "dwc2";
836 phy-names = "usb2-phy";
845 clock-names = "otg";
847 reset-names = "dwc2";
849 phy-names = "usb2-phy";
854 compatible = "snps,dw-wdt";
862 compatible = "snps,dw-wdt";