arm/dts/socfpga.dtsi

4  * SPDX-License-Identifier:	GPL-2.0+
8 #include <dt-bindings/reset/altr,rst-mgr.h>
11 	#address-cells = <1>;
12 	#size-cells = <1>;
29 		#address-cells = <1>;
30 		#size-cells = <0>;
33 			compatible = "arm,cortex-a9";
36 			next-level-cache = <&L2>;
39 			compatible = "arm,cortex-a9";
42 			next-level-cache = <&L2>;
47 		compatible = "arm,cortex-a9-gic";
48 		#interrupt-cells = <3>;
49 		interrupt-controller;
55 		#address-cells = <1>;
56 		#size-cells = <1>;
57 		compatible = "simple-bus";
59 		interrupt-parent = <&intc>;
63 			compatible = "arm,amba-bus";
64 			#address-cells = <1>;
65 			#size-cells = <1>;
79 				#dma-cells = <1>;
80 				#dma-channels = <8>;
81 				#dma-requests = <32>;
83 				clock-names = "apb_pclk";
104 				compatible = "altr,clk-mgr";
108 					#address-cells = <1>;
109 					#size-cells = <0>;
112 						#clock-cells = <0>;
113 						compatible = "fixed-clock";
117 						#clock-cells = <0>;
118 						compatible = "fixed-clock";
122 						#clock-cells = <0>;
123 						compatible = "fixed-clock";
127 						#clock-cells = <0>;
128 						compatible = "fixed-clock";
132 						#address-cells = <1>;
133 						#size-cells = <0>;
134 						#clock-cells = <0>;
135 						compatible = "altr,socfpga-pll-clock";
140 							#clock-cells = <0>;
141 							compatible = "altr,socfpga-perip-clk";
143 							div-reg = <0xe0 0 9>;
148 							#clock-cells = <0>;
149 							compatible = "altr,socfpga-perip-clk";
151 							div-reg = <0xe4 0 9>;
156 							#clock-cells = <0>;
157 							compatible = "altr,socfpga-perip-clk";
159 							div-reg = <0xe8 0 9>;
164 							#clock-cells = <0>;
165 							compatible = "altr,socfpga-perip-clk";
171 							#clock-cells = <0>;
172 							compatible = "altr,socfpga-perip-clk";
178 							#clock-cells = <0>;
179 							compatible = "altr,socfpga-perip-clk";
186 						#address-cells = <1>;
187 						#size-cells = <0>;
188 						#clock-cells = <0>;
189 						compatible = "altr,socfpga-pll-clock";
194 							#clock-cells = <0>;
195 							compatible = "altr,socfpga-perip-clk";
201 							#clock-cells = <0>;
202 							compatible = "altr,socfpga-perip-clk";
208 							#clock-cells = <0>;
209 							compatible = "altr,socfpga-perip-clk";
215 							#clock-cells = <0>;
216 							compatible = "altr,socfpga-perip-clk";
222 							#clock-cells = <0>;
223 							compatible = "altr,socfpga-perip-clk";
229 							#clock-cells = <0>;
230 							compatible = "altr,socfpga-perip-clk";
237 						#address-cells = <1>;
238 						#size-cells = <0>;
239 						#clock-cells = <0>;
240 						compatible = "altr,socfpga-pll-clock";
245 							#clock-cells = <0>;
246 							compatible = "altr,socfpga-perip-clk";
252 							#clock-cells = <0>;
253 							compatible = "altr,socfpga-perip-clk";
259 							#clock-cells = <0>;
260 							compatible = "altr,socfpga-perip-clk";
266 							#clock-cells = <0>;
267 							compatible = "altr,socfpga-perip-clk";
274 						#clock-cells = <0>;
275 						compatible = "altr,socfpga-perip-clk";
277 						fixed-divider = <4>;
281 						#clock-cells = <0>;
282 						compatible = "altr,socfpga-perip-clk";
284 						fixed-divider = <2>;
288 						#clock-cells = <0>;
289 						compatible = "altr,socfpga-gate-clk";
291 						clk-gate = <0x60 0>;
295 						#clock-cells = <0>;
296 						compatible = "altr,socfpga-perip-clk";
298 						fixed-divider = <1>;
302 						#clock-cells = <0>;
303 						compatible = "altr,socfpga-gate-clk";
305 						div-reg = <0x64 0 2>;
306 						clk-gate = <0x60 1>;
310 						#clock-cells = <0>;
311 						compatible = "altr,socfpga-gate-clk";
313 						div-reg = <0x64 2 2>;
317 						#clock-cells = <0>;
318 						compatible = "altr,socfpga-gate-clk";
320 						div-reg = <0x64 4 3>;
321 						clk-gate = <0x60 2>;
325 						#clock-cells = <0>;
326 						compatible = "altr,socfpga-gate-clk";
328 						div-reg = <0x64 7 3>;
329 						clk-gate = <0x60 3>;
333 						#clock-cells = <0>;
334 						compatible = "altr,socfpga-gate-clk";
336 						div-reg = <0x68 0 2>;
337 						clk-gate = <0x60 4>;
341 						#clock-cells = <0>;
342 						compatible = "altr,socfpga-gate-clk";
344 						div-reg = <0x68 2 2>;
345 						clk-gate = <0x60 5>;
349 						#clock-cells = <0>;
350 						compatible = "altr,socfpga-gate-clk";
352 						div-reg = <0x6C 0 3>;
353 						clk-gate = <0x60 6>;
357 						#clock-cells = <0>;
358 						compatible = "altr,socfpga-gate-clk";
360 						clk-gate = <0x60 7>;
364 						#clock-cells = <0>;
365 						compatible = "altr,socfpga-gate-clk";
367 						clk-gate = <0x60 8>;
371 						#clock-cells = <0>;
372 						compatible = "altr,socfpga-gate-clk";
374 						clk-gate = <0x60 9>;
378 						#clock-cells = <0>;
379 						compatible = "altr,socfpga-gate-clk";
381 						clk-gate = <0xa0 0>;
385 						#clock-cells = <0>;
386 						compatible = "altr,socfpga-gate-clk";
388 						clk-gate = <0xa0 1>;
392 						#clock-cells = <0>;
393 						compatible = "altr,socfpga-gate-clk";
395 						clk-gate = <0xa0 2>;
396 						div-reg = <0xa4 0 3>;
400 						#clock-cells = <0>;
401 						compatible = "altr,socfpga-gate-clk";
403 						clk-gate = <0xa0 3>;
404 						div-reg = <0xa4 3 3>;
408 						#clock-cells = <0>;
409 						compatible = "altr,socfpga-gate-clk";
411 						clk-gate = <0xa0 4>;
412 						div-reg = <0xa4 6 3>;
416 						#clock-cells = <0>;
417 						compatible = "altr,socfpga-gate-clk";
419 						clk-gate = <0xa0 5>;
420 						div-reg = <0xa4 9 3>;
424 						#clock-cells = <0>;
425 						compatible = "altr,socfpga-gate-clk";
427 						clk-gate = <0xa0 6>;
428 						div-reg = <0xa8 0 24>;
432 						#clock-cells = <0>;
433 						compatible = "altr,socfpga-gate-clk";
435 						clk-gate = <0xa0 7>;
439 						#clock-cells = <0>;
440 						compatible = "altr,socfpga-gate-clk";
442 						clk-gate = <0xa0 8>;
443 						clk-phase = <0 135>;
447 						#clock-cells = <0>;
448 						compatible = "altr,socfpga-gate-clk";
450 						clk-gate = <0xa0 9>;
454 						#clock-cells = <0>;
455 						compatible = "altr,socfpga-gate-clk";
457 						clk-gate = <0xa0 10>;
458 						fixed-divider = <4>;
462 						#clock-cells = <0>;
463 						compatible = "altr,socfpga-gate-clk";
465 						clk-gate = <0xa0 11>;
471 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
472 			altr,sysmgr-syscon = <&sysmgr 0x60 0>;
475 			interrupt-names = "macirq";
476 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
478 			clock-names = "stmmaceth";
480 			reset-names = "stmmaceth";
481 			snps,multicast-filter-bins = <256>;
482 			snps,perfect-filter-entries = <128>;
487 			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
488 			altr,sysmgr-syscon = <&sysmgr 0x60 2>;
491 			interrupt-names = "macirq";
492 			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
494 			clock-names = "stmmaceth";
496 			reset-names = "stmmaceth";
497 			snps,multicast-filter-bins = <256>;
498 			snps,perfect-filter-entries = <128>;
503 			#address-cells = <1>;
504 			#size-cells = <0>;
505 			compatible = "snps,designware-i2c";
513 			#address-cells = <1>;
514 			#size-cells = <0>;
515 			compatible = "snps,designware-i2c";
523 			#address-cells = <1>;
524 			#size-cells = <0>;
525 			compatible = "snps,designware-i2c";
533 			#address-cells = <1>;
534 			#size-cells = <0>;
535 			compatible = "snps,designware-i2c";
543 			#address-cells = <1>;
544 			#size-cells = <0>;
545 			compatible = "snps,dw-apb-gpio";
550 			porta: gpio-controller@0 {
551 				compatible = "snps,dw-apb-gpio-port";
552 				bank-name = "porta";
553 				gpio-controller;
554 				#gpio-cells = <2>;
555 				snps,nr-gpios = <29>;
557 				interrupt-controller;
558 				#interrupt-cells = <2>;
564 			#address-cells = <1>;
565 			#size-cells = <0>;
566 			compatible = "snps,dw-apb-gpio";
571 			portb: gpio-controller@0 {
572 				compatible = "snps,dw-apb-gpio-port";
573 				bank-name = "portb";
574 				gpio-controller;
575 				#gpio-cells = <2>;
576 				snps,nr-gpios = <29>;
578 				interrupt-controller;
579 				#interrupt-cells = <2>;
585 			#address-cells = <1>;
586 			#size-cells = <0>;
587 			compatible = "snps,dw-apb-gpio";
592 			portc: gpio-controller@0 {
593 				compatible = "snps,dw-apb-gpio-port";
594 				bank-name = "portc";
595 				gpio-controller;
596 				#gpio-cells = <2>;
597 				snps,nr-gpios = <27>;
599 				interrupt-controller;
600 				#interrupt-cells = <2>;
611 			compatible = "altr,sdram-edac";
612 			altr,sdr-syscon = <&sdr>;
616 		L2: l2-cache@fffef000 {
617 			compatible = "arm,pl310-cache";
620 			cache-unified;
621 			cache-level = <2>;
622 			arm,tag-latency = <1 1 1>;
623 			arm,data-latency = <2 1 1>;
627 			compatible = "altr,socfpga-dw-mshc";
630 			fifo-depth = <0x400>;
631 			#address-cells = <1>;
632 			#size-cells = <0>;
634 			clock-names = "biu", "ciu";
639 			#address-cells = <1>;
640 			#size-cells = <0>;
645 			ext-decoder = <0>;  /* external decoder */
646 			num-cs = <4>;
647 			fifo-depth = <128>;
648 			sram-size = <128>;
649 			bus-num = <2>;
654 			compatible = "snps,dw-apb-ssi";
655 			#address-cells = <1>;
656 			#size-cells = <0>;
659 			num-cs = <4>;
660 			bus-num = <0>;
661 			tx-dma-channel = <&pdma 16>;
662 			rx-dma-channel = <&pdma 17>;
668 			compatible = "snps,dw-apb-ssi";
669 			#address-cells = <1>;
670 			#size-cells = <0>;
673 			num-cs = <4>;
674 			bus-num = <1>;
675 			tx-dma-channel = <&pdma 20>;
676 			rx-dma-channel = <&pdma 21>;
683 			compatible = "arm,cortex-a9-twd-timer";
690 			compatible = "snps,dw-apb-timer";
694 			clock-names = "timer";
698 			compatible = "snps,dw-apb-timer";
702 			clock-names = "timer";
706 			compatible = "snps,dw-apb-timer";
710 			clock-names = "timer";
714 			compatible = "snps,dw-apb-timer";
718 			clock-names = "timer";
722 			compatible = "snps,dw-apb-uart";
725 			reg-shift = <2>;
726 			reg-io-width = <4>;
731 			compatible = "snps,dw-apb-uart";
734 			reg-shift = <2>;
735 			reg-io-width = <4>;
740 			#reset-cells = <1>;
741 			compatible = "altr,rst-mgr";
746 			#phy-cells = <0>;
747 			compatible = "usb-nop-xceiv";
756 			clock-names = "otg";
758 			phy-names = "usb2-phy";
767 			clock-names = "otg";
769 			phy-names = "usb2-phy";
774 			compatible = "snps,dw-wdt";
782 			compatible = "snps,dw-wdt";
790 			compatible = "altr,sys-mgr", "syscon";