Lines Matching full:pmucru
710 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
724 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
756 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
769 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
780 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
791 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
802 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
813 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
824 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
835 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
846 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
857 clocks = <&pmucru CLK_SPI0>, <&pmucru PCLK_SPI0>;
875 clocks = <&pmucru CLK_PMUPVTM>, <&pmucru PCLK_PMUPVTM>;
877 resets = <&pmucru SRST_PMUPVTM>,
878 <&pmucru SRST_PMUPVTM_P>;
883 pmucru: clock-controller@ff480000 { label
884 compatible = "rockchip,rv1126-pmucru";
899 <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
900 <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
915 <&pmucru CLK_OSC0_DIV32K>;
940 clocks = <&pmucru CLK_USBPHY_OTG_REF>, <&cru PCLK_USBPHY_OTG>;
963 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>;
985 assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
987 clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
2058 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;