arm/dts/rv1126-u-boot.dtsi

4  * SPDX-License-Identifier:     GPL-2.0+
14 		stdout-path = &uart2;
15 		u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
18 	secure-otp@ff5d0000 {
19 		compatible = "rockchip,rv1126-secure-otp";
22 		u-boot,dm-spl;
28 	u-boot,dm-pre-reloc;
33 	clock-frequency = <24000000>;
34 	u-boot,dm-spl;
35 	/delete-property/ pinctrl-names;
36 	/delete-property/ pinctrl-0;
40 	u-boot,dm-spl;
45 	u-boot,dm-spl;
49 	u-boot,dm-spl;
53 	u-boot,dm-spl;
57 	u-boot,dm-spl;
61 	u-boot,dm-spl;
65 	mmc-ecsd = <0x0020f000>;
66 	u-boot,dm-spl;
67 	/delete-property/ pinctrl-names;
68 	/delete-property/ pinctrl-0;
72 	u-boot,dm-spl;
76 	u-boot,dm-spl;
80 	u-boot,dm-spl;
84 	u-boot,dm-spl;
85 	/delete-property/ assigned-clocks;
86 	/delete-property/ assigned-clock-rates;
87 	/delete-property/ assigned-clock-parents;
91 	u-boot,dm-spl;
96 	u-boot,dm-spl;
100 	u-boot,dm-spl;
105 	u-boot,dm-spl;
106 	/delete-property/ pinctrl-names;
107 	/delete-property/ pinctrl-0;
108 	/delete-property/ assigned-clocks;
109 	/delete-property/ assigned-clock-rates;
112 	#address-cells = <1>;
113 	#size-cells = <0>;
115 		u-boot,dm-spl;
116 		compatible = "spi-nand";
118 		spi-tx-bus-width = <1>;
119 		spi-rx-bus-width = <4>;
120 		spi-max-frequency = <96000000>;
124 		u-boot,dm-spl;
125 		compatible = "jedec,spi-nor";
128 		spi-tx-bus-width = <1>;
129 		spi-rx-bus-width = <4>;
130 		spi-max-frequency = <100000000>;
135 	u-boot,dm-spl;
136 	/delete-property/ pinctrl-names;
137 	/delete-property/ pinctrl-0;
139 	#address-cells = <1>;
140 	#size-cells = <0>;
143 		u-boot,dm-spl;
145 		nand-ecc-mode = "hw";
146 		nand-ecc-strength = <16>;
147 		nand-ecc-step-size = <1024>;
152 	u-boot,dm-spl;
157 	u-boot,dm-spl;
160 		u-boot,dm-spl;
169 	u-boot,dm-pre-reloc;
174 	u-boot,dm-pre-reloc;
179 	u-boot,dm-pre-reloc;
184 	u-boot,dm-pre-reloc;
189 	u-boot,dm-spl;
194 	u-boot,dm-spl;
199 	u-boot,dm-spl;
204 	u-boot,dm-spl;
208 	u-boot,dm-spl;
212 	u-boot,dm-pre-reloc;
217 	u-boot,dm-pre-reloc;
219 	phy-mode = "rgmii";
222 	snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
223 	snps,reset-active-low;
225 	snps,reset-delays-us = <0 20000 100000>;
227 	assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>;
228 	assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
229 	assigned-clock-rates = <125000000>, <0>, <25000000>;
231 	pinctrl-names = "default";
232 	pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
237 	phy-handle = <&phy>;
242 	u-boot,dm-pre-reloc;
246 		compatible = "ethernet-phy-ieee802.3-c22";
247 		u-boot,dm-pre-reloc;
254 	u-boot,dm-pre-reloc;
257 		u-boot,dm-pre-reloc;
262 	u-boot,dm-pre-reloc;
265 		u-boot,dm-pre-reloc;
270 	u-boot,dm-pre-reloc;
275 	u-boot,dm-pre-reloc;
280 	u-boot,dm-pre-reloc;
285 	u-boot,dm-pre-reloc;
290 	u-boot,dm-spl;
295 	u-boot,dm-pre-reloc;
300 	u-boot,dm-pre-reloc;
305 	u-boot,dm-pre-reloc;
310 	u-boot,dm-pre-reloc;