Lines Matching +full:2 +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include "rockchip-pinconf.dtsi"
11 a7m0_pins: a7m0-pins {
14 <1 RK_PA6 3 &pcfg_pull_none>,
16 <1 RK_PA7 3 &pcfg_pull_none>;
18 a7m1_pins: a7m1-pins {
21 <3 RK_PA2 2 &pcfg_pull_none>,
23 <3 RK_PA3 2 &pcfg_pull_none>;
27 acodec_pins: acodec-pins {
30 <3 RK_PD1 4 &pcfg_pull_none>,
32 <3 RK_PD7 3 &pcfg_pull_none>,
34 <3 RK_PD4 3 &pcfg_pull_none>,
36 <3 RK_PD0 3 &pcfg_pull_none>,
38 <3 RK_PD6 3 &pcfg_pull_none>,
40 <3 RK_PD5 3 &pcfg_pull_none>,
42 <3 RK_PD3 3 &pcfg_pull_none>;
46 auddsm_pins: auddsm-pins {
49 <3 RK_PD3 5 &pcfg_pull_none>,
51 <3 RK_PD5 5 &pcfg_pull_none>,
59 audpwmm0_pins: audpwmm0-pins {
62 <4 RK_PA0 3 &pcfg_pull_none>,
64 <4 RK_PA1 3 &pcfg_pull_none>;
66 audpwmm1_pins: audpwmm1-pins {
69 <3 RK_PD3 4 &pcfg_pull_none>,
71 <3 RK_PD5 4 &pcfg_pull_none>;
75 canm0_pins: canm0-pins {
78 <3 RK_PA0 3 &pcfg_pull_none>,
80 <3 RK_PA1 3 &pcfg_pull_none>;
82 canm1_pins: canm1-pins {
85 <3 RK_PA6 5 &pcfg_pull_none>,
87 <3 RK_PA7 5 &pcfg_pull_none>;
91 cifm0_dvp_ctl: cifm0-dvp_ctl {
94 <3 RK_PC5 1 &pcfg_pull_none>,
96 <3 RK_PC6 1 &pcfg_pull_none>,
98 <3 RK_PA4 1 &pcfg_pull_none>,
100 <3 RK_PB6 1 &pcfg_pull_none>,
102 <3 RK_PB7 1 &pcfg_pull_none>,
104 <3 RK_PC0 1 &pcfg_pull_none>,
106 <3 RK_PC1 1 &pcfg_pull_none>,
108 <3 RK_PC2 1 &pcfg_pull_none>,
110 <3 RK_PC3 1 &pcfg_pull_none>,
112 <3 RK_PA5 1 &pcfg_pull_none>,
114 <3 RK_PA6 1 &pcfg_pull_none>,
116 <3 RK_PA7 1 &pcfg_pull_none>,
118 <3 RK_PB0 1 &pcfg_pull_none>,
120 <3 RK_PB1 1 &pcfg_pull_none>,
122 <3 RK_PB2 1 &pcfg_pull_none>,
124 <3 RK_PB3 1 &pcfg_pull_none>,
126 <3 RK_PB4 1 &pcfg_pull_none>,
128 <3 RK_PB5 1 &pcfg_pull_none>,
130 <3 RK_PC7 1 &pcfg_pull_none>,
132 <3 RK_PC4 1 &pcfg_pull_none>;
134 cifm1_dvp_ctl: cifm1-dvp_ctl {
137 <2 RK_PD2 3 &pcfg_pull_none>,
139 <2 RK_PD1 3 &pcfg_pull_none>,
141 <2 RK_PA4 3 &pcfg_pull_none>,
143 <2 RK_PC2 3 &pcfg_pull_none>,
145 <2 RK_PC3 3 &pcfg_pull_none>,
147 <2 RK_PC4 3 &pcfg_pull_none>,
149 <2 RK_PC5 3 &pcfg_pull_none>,
151 <2 RK_PC6 3 &pcfg_pull_none>,
153 <2 RK_PC7 3 &pcfg_pull_none>,
155 <2 RK_PA5 3 &pcfg_pull_none>,
157 <2 RK_PA6 3 &pcfg_pull_none>,
159 <2 RK_PB3 3 &pcfg_pull_none>,
161 <2 RK_PB4 3 &pcfg_pull_none>,
163 <2 RK_PB5 3 &pcfg_pull_none>,
165 <2 RK_PB6 3 &pcfg_pull_none>,
167 <2 RK_PB7 3 &pcfg_pull_none>,
169 <2 RK_PC0 3 &pcfg_pull_none>,
171 <2 RK_PC1 3 &pcfg_pull_none>,
173 <2 RK_PD3 3 &pcfg_pull_none>,
175 <2 RK_PD0 3 &pcfg_pull_none>;
179 clkm0_pins: clkm0-pins {
182 <3 RK_PC5 2 &pcfg_pull_none>;
184 clkm1_pins: clkm1-pins {
187 <2 RK_PC5 2 &pcfg_pull_none>;
189 clk_32k: clk-32k {
193 clk_ref: clk-ref {
199 emmc_rstnout: emmc-rstnout {
202 <1 RK_PA3 2 &pcfg_pull_none>;
204 emmc_bus8: emmc-bus8 {
207 <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
209 <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
211 <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
213 <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
215 <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
217 <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
219 <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
221 <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
223 emmc_clk: emmc-clk {
226 <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
228 emmc_cmd: emmc-cmd {
231 <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
235 flash_pins: flash-pins {
276 fspi_pins: fspi-pins {
279 <1 RK_PA3 3 &pcfg_pull_down>,
281 <0 RK_PD4 3 &pcfg_pull_up>,
283 <1 RK_PA0 3 &pcfg_pull_up>,
285 <1 RK_PA1 3 &pcfg_pull_up>,
287 <0 RK_PD6 3 &pcfg_pull_up>,
289 <1 RK_PA2 3 &pcfg_pull_up>;
291 fspi_cs1: fspi-cs1 {
294 <1 RK_PD1 3 &pcfg_pull_up>;
298 i2c0_xfer: i2c0-xfer {
307 i2c1_xfer: i2c1-xfer {
316 i2c2_xfer: i2c2-xfer {
325 i2c3m0_xfer: i2c3m0-xfer {
328 <3 RK_PA4 5 &pcfg_pull_none_smt>,
330 <3 RK_PA5 5 &pcfg_pull_none_smt>;
332 i2c3m1_xfer: i2c3m1-xfer {
335 <2 RK_PD4 7 &pcfg_pull_none_smt>,
337 <2 RK_PD5 7 &pcfg_pull_none_smt>;
339 i2c3m2_xfer: i2c3m2-xfer {
342 <1 RK_PD6 3 &pcfg_pull_none_smt>,
344 <1 RK_PD7 3 &pcfg_pull_none_smt>;
348 i2c4m0_xfer: i2c4m0-xfer {
351 <3 RK_PA0 7 &pcfg_pull_none_smt>,
353 <3 RK_PA1 7 &pcfg_pull_none_smt>;
355 i2c4m1_xfer: i2c4m1-xfer {
364 i2c5m0_xfer: i2c5m0-xfer {
367 <2 RK_PA5 7 &pcfg_pull_none_smt>,
369 <2 RK_PB3 7 &pcfg_pull_none_smt>;
371 i2c5m1_xfer: i2c5m1-xfer {
374 <3 RK_PB0 5 &pcfg_pull_none_smt>,
376 <3 RK_PB1 5 &pcfg_pull_none_smt>;
378 i2c5m2_xfer: i2c5m2-xfer {
387 i2s0m0_lrck_rx: i2s0m0-lrck-rx {
389 <3 RK_PD4 1 &pcfg_pull_none>;
391 i2s0m0_lrck_tx: i2s0m0-lrck-tx {
393 <3 RK_PD3 1 &pcfg_pull_none>;
395 i2s0m0_mclk: i2s0m0-mclk {
397 <3 RK_PD2 1 &pcfg_pull_none>;
399 i2s0m0_sclk_rx: i2s0m0-sclk-rx {
401 <3 RK_PD1 1 &pcfg_pull_none>;
403 i2s0m0_sclk_tx: i2s0m0-sclk-tx {
405 <3 RK_PD0 1 &pcfg_pull_none>;
407 i2s0m0_sdi0: i2s0m0-sdi0 {
409 <3 RK_PD6 1 &pcfg_pull_none>;
411 i2s0m0_sdo0: i2s0m0-sdo0 {
413 <3 RK_PD5 1 &pcfg_pull_none>;
415 i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 {
417 <3 RK_PD7 1 &pcfg_pull_none>;
419 i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 {
423 i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 {
427 i2s0m1_lrck_rx: i2s0m1-lrck-rx {
429 <3 RK_PB2 3 &pcfg_pull_none>;
431 i2s0m1_lrck_tx: i2s0m1-lrck-tx {
433 <3 RK_PA5 3 &pcfg_pull_none>;
435 i2s0m1_mclk: i2s0m1-mclk {
437 <3 RK_PB0 3 &pcfg_pull_none>;
439 i2s0m1_sclk_rx: i2s0m1-sclk-rx {
441 <3 RK_PB1 3 &pcfg_pull_none>;
443 i2s0m1_sclk_tx: i2s0m1-sclk-tx {
445 <3 RK_PA4 3 &pcfg_pull_none>;
447 i2s0m1_sdi0: i2s0m1-sdi0 {
449 <3 RK_PA7 3 &pcfg_pull_none>;
451 i2s0m1_sdo0: i2s0m1-sdo0 {
453 <3 RK_PA6 3 &pcfg_pull_none>;
455 i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 {
457 <3 RK_PB3 3 &pcfg_pull_none>;
459 i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 {
461 <3 RK_PB4 3 &pcfg_pull_none>;
463 i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 {
465 <3 RK_PB5 3 &pcfg_pull_none>;
469 i2s1m0_lrck: i2s1m0-lrck {
473 i2s1m0_mclk: i2s1m0-mclk {
477 i2s1m0_sclk: i2s1m0-sclk {
481 i2s1m0_sdi: i2s1m0-sdi {
485 i2s1m0_sdo: i2s1m0-sdo {
489 i2s1m1_lrck: i2s1m1-lrck {
491 <1 RK_PD7 2 &pcfg_pull_none>;
493 i2s1m1_mclk: i2s1m1-mclk {
495 <1 RK_PD5 2 &pcfg_pull_none>;
497 i2s1m1_sclk: i2s1m1-sclk {
499 <1 RK_PD6 2 &pcfg_pull_none>;
501 i2s1m1_sdi: i2s1m1-sdi {
503 <2 RK_PA0 2 &pcfg_pull_none>;
505 i2s1m1_sdo: i2s1m1-sdo {
507 <2 RK_PA1 2 &pcfg_pull_none>;
509 i2s1m2_lrck: i2s1m2-lrck {
511 <2 RK_PD2 6 &pcfg_pull_none>;
513 i2s1m2_mclk: i2s1m2-mclk {
515 <2 RK_PC7 6 &pcfg_pull_none>;
517 i2s1m2_sclk: i2s1m2-sclk {
519 <2 RK_PD1 6 &pcfg_pull_none>;
521 i2s1m2_sdi: i2s1m2-sdi {
523 <2 RK_PD3 6 &pcfg_pull_none>;
525 i2s1m2_sdo: i2s1m2-sdo {
527 <2 RK_PD0 6 &pcfg_pull_none>;
531 i2s2m0_lrck: i2s2m0-lrck {
535 i2s2m0_mclk: i2s2m0-mclk {
539 i2s2m0_sclk: i2s2m0-sclk {
543 i2s2m0_sdi: i2s2m0-sdi {
547 i2s2m0_sdo: i2s2m0-sdo {
551 i2s2m1_lrck: i2s2m1-lrck {
553 <2 RK_PB2 2 &pcfg_pull_none>;
555 i2s2m1_mclk: i2s2m1-mclk {
557 <2 RK_PB3 2 &pcfg_pull_none>;
559 i2s2m1_sclk: i2s2m1-sclk {
561 <2 RK_PB1 2 &pcfg_pull_none>;
563 i2s2m1_sdi: i2s2m1-sdi {
565 <2 RK_PB0 2 &pcfg_pull_none>;
567 i2s2m1_sdo: i2s2m1-sdo {
569 <2 RK_PA7 2 &pcfg_pull_none>;
573 lcdc_ctl: lcdc-ctl {
576 <2 RK_PD7 1 &pcfg_pull_none>,
578 <2 RK_PA4 1 &pcfg_pull_none>,
580 <2 RK_PA5 1 &pcfg_pull_none>,
582 <2 RK_PB6 1 &pcfg_pull_none>,
584 <2 RK_PB7 1 &pcfg_pull_none>,
586 <2 RK_PC0 1 &pcfg_pull_none>,
588 <2 RK_PC1 1 &pcfg_pull_none>,
590 <2 RK_PC2 1 &pcfg_pull_none>,
592 <2 RK_PC3 1 &pcfg_pull_none>,
594 <2 RK_PC4 1 &pcfg_pull_none>,
596 <2 RK_PC5 1 &pcfg_pull_none>,
598 <2 RK_PC6 1 &pcfg_pull_none>,
600 <2 RK_PC7 1 &pcfg_pull_none>,
602 <2 RK_PA6 1 &pcfg_pull_none>,
604 <2 RK_PD0 1 &pcfg_pull_none>,
606 <2 RK_PD1 1 &pcfg_pull_none>,
608 <2 RK_PD2 1 &pcfg_pull_none>,
610 <2 RK_PD3 1 &pcfg_pull_none>,
612 <2 RK_PA7 1 &pcfg_pull_none>,
614 <2 RK_PB0 1 &pcfg_pull_none>,
616 <2 RK_PB1 1 &pcfg_pull_none>,
618 <2 RK_PB2 1 &pcfg_pull_none>,
620 <2 RK_PB3 1 &pcfg_pull_none>,
622 <2 RK_PB4 1 &pcfg_pull_none>,
624 <2 RK_PB5 1 &pcfg_pull_none>,
626 <2 RK_PD4 1 &pcfg_pull_none>,
628 <2 RK_PD5 1 &pcfg_pull_none>,
630 <2 RK_PD6 1 &pcfg_pull_none>;
634 mcu_pins: mcu-pins {
649 mipim1_pins: mipim1-pins {
652 <2 RK_PA2 1 &pcfg_pull_none>;
654 mipi_csi_clk0: mipi-csi-clk0 {
656 <2 RK_PA3 1 &pcfg_pull_none>;
660 pdmm0_clk: pdmm0-clk {
663 <3 RK_PD4 2 &pcfg_pull_none>;
665 pdmm0_clk1: pdmm0-clk1 {
667 <3 RK_PD1 2 &pcfg_pull_none>;
669 pdmm0_sdi0: pdmm0-sdi0 {
671 <3 RK_PD6 2 &pcfg_pull_none>;
673 pdmm0_sdi1: pdmm0-sdi1 {
675 <4 RK_PA1 2 &pcfg_pull_none>;
677 pdmm0_sdi2: pdmm0-sdi2 {
679 <4 RK_PA0 2 &pcfg_pull_none>;
681 pdmm0_sdi3: pdmm0-sdi3 {
683 <3 RK_PD7 2 &pcfg_pull_none>;
685 pdmm1_clk: pdmm1-clk {
688 <3 RK_PC0 3 &pcfg_pull_none>;
690 pdmm1_clk1: pdmm1-clk1 {
692 <3 RK_PC3 3 &pcfg_pull_none>;
694 pdmm1_sdi0: pdmm1-sdi0 {
696 <3 RK_PC1 3 &pcfg_pull_none>;
698 pdmm1_sdi1: pdmm1-sdi1 {
700 <3 RK_PC2 3 &pcfg_pull_none>;
702 pdmm1_sdi2: pdmm1-sdi2 {
704 <3 RK_PB6 3 &pcfg_pull_none>;
706 pdmm1_sdi3: pdmm1-sdi3 {
708 <3 RK_PB7 3 &pcfg_pull_none>;
712 pmic_pins: pmic-pins {
721 pmu_pins: pmu-pins {
728 prelight_pins: prelight-pins {
735 pwm0m0_pins: pwm0m0-pins {
738 <0 RK_PB6 3 &pcfg_pull_none>;
740 pwm0m0_pins_pull_down: pwm0m0-pins-pull-down {
743 <0 RK_PB6 3 &pcfg_pull_down>;
745 pwm0m1_pins: pwm0m1-pins {
748 <2 RK_PB3 5 &pcfg_pull_none>;
750 pwm0m1_pins_pull_down: pwm0m1-pins-pull-down {
753 <2 RK_PB3 5 &pcfg_pull_down>;
757 pwm1m0_pins: pwm1m0-pins {
760 <0 RK_PB7 3 &pcfg_pull_none>;
762 pwm1m0_pins_pull_down: pwm1m0-pins-pull-down {
765 <0 RK_PB7 3 &pcfg_pull_down>;
767 pwm1m1_pins: pwm1m1-pins {
770 <2 RK_PB2 5 &pcfg_pull_none>;
772 pwm1m1_pins_pull_down: pwm1m1-pins-pull-down {
775 <2 RK_PB2 5 &pcfg_pull_down>;
779 pwm10m0_pins: pwm10m0-pins {
782 <3 RK_PA6 6 &pcfg_pull_none>;
784 pwm10m0_pins_pull_down: pwm10m0-pins-pull-down {
787 <3 RK_PA6 6 &pcfg_pull_down>;
789 pwm10m1_pins: pwm10m1-pins {
792 <2 RK_PD5 5 &pcfg_pull_none>;
794 pwm10m1_pins_pull_down: pwm10m1-pins-pull-down {
797 <2 RK_PD5 5 &pcfg_pull_down>;
801 pwm11m0_pins: pwm11m0-pins {
804 <3 RK_PA7 6 &pcfg_pull_none>;
806 pwm11m0_pins_pull_down: pwm11m0-pins-pull-down {
809 <3 RK_PA7 6 &pcfg_pull_down>;
811 pwm11m1_pins: pwm11m1-pins {
814 <2 RK_PD4 5 &pcfg_pull_none>;
816 pwm11m1_pins_pull_down: pwm11m1-pins-pull-down {
819 <2 RK_PD4 5 &pcfg_pull_down>;
823 pwm2m0_pins: pwm2m0-pins {
826 <0 RK_PC0 3 &pcfg_pull_none>;
828 pwm2m0_pins_pull_down: pwm2m0-pins-pull-down {
831 <0 RK_PC0 3 &pcfg_pull_down>;
833 pwm2m1_pins: pwm2m1-pins {
836 <2 RK_PB1 5 &pcfg_pull_none>;
838 pwm2m1_pins_pull_down: pwm2m1-pins-pull-down {
841 <2 RK_PB1 5 &pcfg_pull_down>;
845 pwm3m0_pins: pwm3m0-pins {
848 <0 RK_PC1 3 &pcfg_pull_none>;
850 pwm3m0_pins_pull_down: pwm3m0-pins-pull-down {
853 <0 RK_PC1 3 &pcfg_pull_down>;
855 pwm3m1_pins: pwm3m1-pins {
858 <2 RK_PB0 5 &pcfg_pull_none>;
860 pwm3m1_pins_pull_down: pwm3m1-pins-pull-down {
863 <2 RK_PB0 5 &pcfg_pull_down>;
867 pwm4m0_pins: pwm4m0-pins {
870 <0 RK_PC2 3 &pcfg_pull_none>;
872 pwm4m0_pins_pull_down: pwm4m0-pins-pull-down {
875 <0 RK_PC2 3 &pcfg_pull_down>;
877 pwm4m1_pins: pwm4m1-pins {
880 <2 RK_PA7 5 &pcfg_pull_none>;
882 pwm4m1_pins_pull_down: pwm4m1-pins-pull-down {
885 <2 RK_PA7 5 &pcfg_pull_down>;
889 pwm5m0_pins: pwm5m0-pins {
892 <0 RK_PC3 3 &pcfg_pull_none>;
894 pwm5m0_pins_pull_down: pwm5m0-pins-pull-down {
897 <0 RK_PC3 3 &pcfg_pull_down>;
899 pwm5m1_pins: pwm5m1-pins {
902 <2 RK_PA6 5 &pcfg_pull_none>;
904 pwm5m1_pins_pull_down: pwm5m1-pins-pull-down {
907 <2 RK_PA6 5 &pcfg_pull_down>;
911 pwm6m0_pins: pwm6m0-pins {
914 <0 RK_PB2 3 &pcfg_pull_none>;
916 pwm6m0_pins_pull_down: pwm6m0-pins-pull-down {
919 <0 RK_PB2 3 &pcfg_pull_down>;
921 pwm6m1_pins: pwm6m1-pins {
924 <3 RK_PA1 5 &pcfg_pull_none>;
926 pwm6m1_pins_pull_up: pwm6m1-pins-pull-up {
929 <3 RK_PA1 5 &pcfg_pull_up>;
933 pwm7m0_pins: pwm7m0-pins {
936 <0 RK_PB1 3 &pcfg_pull_none>;
938 pwm7m0_pins_pull_down: pwm7m0-pins-pull-down {
941 <0 RK_PB1 3 &pcfg_pull_down>;
943 pwm7m1_pins: pwm7m1-pins {
946 <3 RK_PA0 5 &pcfg_pull_none>;
948 pwm7m1_pins_pull_up: pwm7m1-pins-pull-up {
951 <3 RK_PA0 5 &pcfg_pull_up>;
955 pwm8m0_pins: pwm8m0-pins {
958 <3 RK_PA4 6 &pcfg_pull_none>;
960 pwm8m0_pins_pull_down: pwm8m0-pins-pull-down {
963 <3 RK_PA4 6 &pcfg_pull_down>;
965 pwm8m1_pins: pwm8m1-pins {
968 <2 RK_PD7 5 &pcfg_pull_none>;
970 pwm8m1_pins_pull_down: pwm8m1-pins-pull-down {
973 <2 RK_PD7 5 &pcfg_pull_down>;
977 pwm9m0_pins: pwm9m0-pins {
980 <3 RK_PA5 6 &pcfg_pull_none>;
982 pwm9m0_pins_pull_down: pwm9m0-pins-pull-down {
985 <3 RK_PA5 6 &pcfg_pull_down>;
987 pwm9m1_pins: pwm9m1-pins {
990 <2 RK_PD6 5 &pcfg_pull_none>;
992 pwm9m1_pins_pull_down: pwm9m1-pins-pull-down {
995 <2 RK_PD6 5 &pcfg_pull_down>;
999 rgmiim0_pins: rgmiim0-pins {
1002 <3 RK_PC0 2 &pcfg_pull_none>,
1004 <3 RK_PC4 2 &pcfg_pull_none>,
1006 <3 RK_PC3 2 &pcfg_pull_none>,
1008 <3 RK_PC7 2 &pcfg_pull_none>,
1010 <3 RK_PB6 2 &pcfg_pull_none>,
1012 <3 RK_PB7 2 &pcfg_pull_none>,
1014 <3 RK_PA7 2 &pcfg_pull_none>,
1016 <3 RK_PB0 2 &pcfg_pull_none>,
1018 <3 RK_PC1 2 &pcfg_pull_none>,
1020 <3 RK_PC6 2 &pcfg_pull_none_drv_level_12>,
1022 <3 RK_PB3 2 &pcfg_pull_none_drv_level_12>,
1024 <3 RK_PB4 2 &pcfg_pull_none_drv_level_12>,
1026 <3 RK_PB1 2 &pcfg_pull_none_drv_level_12>,
1028 <3 RK_PB2 2 &pcfg_pull_none_drv_level_12>,
1030 <3 RK_PB5 2 &pcfg_pull_none_drv_level_12>;
1032 rgmiim1_pins: rgmiim1-pins {
1035 <2 RK_PB7 2 &pcfg_pull_none>,
1037 <2 RK_PC2 2 &pcfg_pull_none>,
1039 <2 RK_PC1 2 &pcfg_pull_none>,
1041 <2 RK_PD3 2 &pcfg_pull_none>,
1043 <2 RK_PB5 2 &pcfg_pull_none>,
1045 <2 RK_PB6 2 &pcfg_pull_none>,
1047 <2 RK_PC7 2 &pcfg_pull_none>,
1049 <2 RK_PD0 2 &pcfg_pull_none>,
1051 <2 RK_PB4 2 &pcfg_pull_none>,
1053 <2 RK_PD2 2 &pcfg_pull_none_drv_level_12>,
1055 <2 RK_PC3 2 &pcfg_pull_none_drv_level_12>,
1057 <2 RK_PC4 2 &pcfg_pull_none_drv_level_12>,
1059 <2 RK_PD1 2 &pcfg_pull_none_drv_level_12>,
1061 <2 RK_PA4 2 &pcfg_pull_none_drv_level_12>,
1063 <2 RK_PC6 2 &pcfg_pull_none_drv_level_12>;
1067 rmiim0_pins: rmiim0-pins {
1070 <3 RK_PC0 2 &pcfg_pull_none>,
1072 <3 RK_PC4 2 &pcfg_pull_none>,
1074 <3 RK_PC3 2 &pcfg_pull_none>,
1076 <3 RK_PB6 2 &pcfg_pull_none>,
1078 <3 RK_PB7 2 &pcfg_pull_none>,
1080 <3 RK_PC1 2 &pcfg_pull_none>,
1082 <3 RK_PC2 2 &pcfg_pull_none>,
1084 <3 RK_PB3 2 &pcfg_pull_none_drv_level_12>,
1086 <3 RK_PB4 2 &pcfg_pull_none_drv_level_12>,
1088 <3 RK_PB5 2 &pcfg_pull_none_drv_level_12>;
1090 rmiim1_pins: rmiim1-pins {
1093 <2 RK_PB7 2 &pcfg_pull_none>,
1095 <2 RK_PC2 2 &pcfg_pull_none>,
1097 <2 RK_PC1 2 &pcfg_pull_none>,
1099 <2 RK_PB5 2 &pcfg_pull_none>,
1101 <2 RK_PB6 2 &pcfg_pull_none>,
1103 <2 RK_PB4 2 &pcfg_pull_none>,
1105 <2 RK_PC0 2 &pcfg_pull_none>,
1107 <2 RK_PC3 2 &pcfg_pull_none_drv_level_12>,
1109 <2 RK_PC4 2 &pcfg_pull_none_drv_level_12>,
1111 <2 RK_PC6 2 &pcfg_pull_none_drv_level_12>;
1115 clk_out_ethernetm0_pins: clk-out-ethernetm0-pins {
1118 <3 RK_PC5 2 &pcfg_pull_none>;
1120 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
1123 <2 RK_PC5 2 &pcfg_pull_none>;
1127 sdmmc0_bus4: sdmmc0-bus4 {
1138 sdmmc0_clk: sdmmc0-clk {
1143 sdmmc0_cmd: sdmmc0-cmd {
1148 sdmmc0_det: sdmmc0-det {
1152 sdmmc0_pwr: sdmmc0-pwr {
1158 sdmmc1_bus4: sdmmc1-bus4 {
1169 sdmmc1_clk: sdmmc1-clk {
1174 sdmmc1_cmd: sdmmc1-cmd {
1179 sdmmc1_det: sdmmc1-det {
1181 <1 RK_PD0 2 &pcfg_pull_none>;
1183 sdmmc1_pwr: sdmmc1-pwr {
1185 <1 RK_PD1 2 &pcfg_pull_none>;
1189 spi0m0_clk: spi0m0-clk {
1193 spi0m0_cs0n: spi0m0-cs0n {
1197 spi0m0_cs1n: spi0m0-cs1n {
1201 spi0m0_miso: spi0m0-miso {
1205 spi0m0_mosi: spi0m0-mosi {
1209 spi0m0_clk_hs: spi0m0-clk_hs {
1213 spi0m0_miso_hs: spi0m0-miso_hs {
1217 spi0m0_mosi_hs: spi0m0-mosi_hs {
1221 spi0m1_clk: spi0m1-clk {
1223 <2 RK_PA1 1 &pcfg_pull_none>;
1225 spi0m1_cs0n: spi0m1-cs0n {
1227 <2 RK_PA0 1 &pcfg_pull_none>;
1229 spi0m1_cs1n: spi0m1-cs1n {
1233 spi0m1_miso: spi0m1-miso {
1237 spi0m1_mosi: spi0m1-mosi {
1241 spi0m2_clk: spi0m2-clk {
1243 <2 RK_PB2 6 &pcfg_pull_none>;
1245 spi0m2_cs0n: spi0m2-cs0n {
1247 <2 RK_PA7 6 &pcfg_pull_none>;
1249 spi0m2_cs1n: spi0m2-cs1n {
1251 <2 RK_PB3 6 &pcfg_pull_none>;
1253 spi0m2_miso: spi0m2-miso {
1255 <2 RK_PB1 6 &pcfg_pull_none>;
1257 spi0m2_mosi: spi0m2-mosi {
1259 <2 RK_PB0 6 &pcfg_pull_none>;
1263 spi1m0_clk: spi1m0-clk {
1265 <3 RK_PC0 5 &pcfg_pull_none>;
1267 spi1m0_cs0n: spi1m0-cs0n {
1269 <3 RK_PB5 5 &pcfg_pull_none>;
1271 spi1m0_cs1n: spi1m0-cs1n {
1273 <3 RK_PB4 5 &pcfg_pull_none>;
1275 spi1m0_miso: spi1m0-miso {
1277 <3 RK_PB7 5 &pcfg_pull_none>;
1279 spi1m0_mosi: spi1m0-mosi {
1281 <3 RK_PB6 5 &pcfg_pull_none>;
1283 spi1m0_clk_hs: spi1m0-clk_hs {
1285 <3 RK_PC0 5 &pcfg_pull_up_drv_level_2>;
1287 spi1m0_miso_hs: spi1m0-miso_hs {
1289 <3 RK_PB7 5 &pcfg_pull_up_drv_level_2>;
1291 spi1m0_mosi_hs: spi1m0-mosi_hs {
1293 <3 RK_PB6 5 &pcfg_pull_up_drv_level_2>;
1295 spi1m1_clk: spi1m1-clk {
1297 <1 RK_PC6 3 &pcfg_pull_none>;
1299 spi1m1_cs0n: spi1m1-cs0n {
1301 <1 RK_PC7 3 &pcfg_pull_none>;
1303 spi1m1_cs1n: spi1m1-cs1n {
1305 <1 RK_PD0 3 &pcfg_pull_none>;
1307 spi1m1_miso: spi1m1-miso {
1309 <1 RK_PC5 3 &pcfg_pull_none>;
1311 spi1m1_mosi: spi1m1-mosi {
1313 <1 RK_PC4 3 &pcfg_pull_none>;
1315 spi1m2_clk: spi1m2-clk {
1317 <2 RK_PD5 6 &pcfg_pull_none>;
1319 spi1m2_cs0n: spi1m2-cs0n {
1321 <2 RK_PD4 6 &pcfg_pull_none>;
1323 spi1m2_cs1n: spi1m2-cs1n {
1325 <3 RK_PA0 6 &pcfg_pull_none>;
1327 spi1m2_miso: spi1m2-miso {
1329 <2 RK_PD7 6 &pcfg_pull_none>;
1331 spi1m2_mosi: spi1m2-mosi {
1333 <2 RK_PD6 6 &pcfg_pull_none>;
1337 tsadcm0_pins: tsadcm0-pins {
1342 tsadcm1_pins: tsadcm1-pins {
1345 <0 RK_PB2 2 &pcfg_pull_none>;
1347 tsadc_shutorg: tsadc-shutorg {
1349 <0 RK_PA1 2 &pcfg_pull_none>;
1353 uart0_xfer: uart0-xfer {
1360 uart0_ctsn: uart0-ctsn {
1364 uart0_rtsn: uart0-rtsn {
1370 uart1m0_xfer: uart1m0-xfer {
1373 <0 RK_PB7 2 &pcfg_pull_up>,
1375 <0 RK_PB6 2 &pcfg_pull_up>;
1377 uart1m0_ctsn: uart1m0-ctsn {
1379 <0 RK_PC1 2 &pcfg_pull_none>;
1381 uart1m0_rtsn: uart1m0-rtsn {
1383 <0 RK_PC0 2 &pcfg_pull_none>;
1385 uart1m1_xfer: uart1m1-xfer {
1392 uart1m1_ctsn: uart1m1-ctsn {
1396 uart1m1_rtsn: uart1m1-rtsn {
1402 uart2m0_xfer: uart2m0-xfer {
1405 <1 RK_PA4 3 &pcfg_pull_up>,
1407 <1 RK_PA5 3 &pcfg_pull_up>;
1409 uart2m1_xfer: uart2m1-xfer {
1412 <3 RK_PA3 1 &pcfg_pull_up>,
1414 <3 RK_PA2 1 &pcfg_pull_up>;
1418 uart3m0_xfer: uart3m0-xfer {
1421 <3 RK_PC7 4 &pcfg_pull_up>,
1423 <3 RK_PC6 4 &pcfg_pull_up>;
1425 uart3m0_ctsn: uart3m0-ctsn {
1427 <3 RK_PC5 4 &pcfg_pull_none>;
1429 uart3m0_rtsn: uart3m0-rtsn {
1431 <3 RK_PC4 4 &pcfg_pull_none>;
1433 uart3m1_xfer: uart3m1-xfer {
1436 <1 RK_PA6 2 &pcfg_pull_up>,
1438 <1 RK_PA7 2 &pcfg_pull_up>;
1440 uart3m2_xfer: uart3m2-xfer {
1443 <3 RK_PA1 4 &pcfg_pull_up>,
1445 <3 RK_PA0 4 &pcfg_pull_up>;
1447 uart3m2_ctsn: uart3m2-ctsn {
1449 <2 RK_PD7 4 &pcfg_pull_none>;
1451 uart3m2_rtsn: uart3m2-rtsn {
1453 <2 RK_PD6 4 &pcfg_pull_none>;
1455 uart3_ctsn: uart3-ctsn {
1457 <1 RK_PB1 2 &pcfg_pull_none>;
1459 uart3_rtsn: uart3-rtsn {
1461 <1 RK_PB0 2 &pcfg_pull_none>;
1465 uart4m0_xfer: uart4m0-xfer {
1468 <3 RK_PA5 4 &pcfg_pull_up>,
1470 <3 RK_PA4 4 &pcfg_pull_up>;
1472 uart4m0_ctsn: uart4m0-ctsn {
1474 <3 RK_PB3 4 &pcfg_pull_none>;
1476 uart4m0_rtsn: uart4m0-rtsn {
1478 <3 RK_PB2 4 &pcfg_pull_none>;
1480 uart4m1_xfer: uart4m1-xfer {
1483 <2 RK_PA7 4 &pcfg_pull_up>,
1485 <2 RK_PA6 4 &pcfg_pull_up>;
1487 uart4m1_ctsn: uart4m1-ctsn {
1489 <2 RK_PA5 4 &pcfg_pull_none>;
1491 uart4m1_rtsn: uart4m1-rtsn {
1493 <2 RK_PA4 4 &pcfg_pull_none>;
1495 uart4m2_xfer: uart4m2-xfer {
1498 <1 RK_PD4 3 &pcfg_pull_up>,
1500 <1 RK_PD5 3 &pcfg_pull_up>;
1502 uart4m2_ctsn: uart4m2-ctsn {
1504 <1 RK_PD3 3 &pcfg_pull_none>;
1506 uart4m2_rtsn: uart4m2-rtsn {
1508 <1 RK_PD2 3 &pcfg_pull_none>;
1512 uart5m0_xfer: uart5m0-xfer {
1515 <3 RK_PA7 4 &pcfg_pull_up>,
1517 <3 RK_PA6 4 &pcfg_pull_up>;
1519 uart5m0_ctsn: uart5m0-ctsn {
1521 <3 RK_PB1 4 &pcfg_pull_none>;
1523 uart5m0_rtsn: uart5m0-rtsn {
1525 <3 RK_PB0 4 &pcfg_pull_none>;
1527 uart5m1_xfer: uart5m1-xfer {
1530 <2 RK_PB1 4 &pcfg_pull_up>,
1532 <2 RK_PB0 4 &pcfg_pull_up>;
1534 uart5m1_ctsn: uart5m1-ctsn {
1536 <2 RK_PB3 4 &pcfg_pull_none>;
1538 uart5m1_rtsn: uart5m1-rtsn {
1540 <2 RK_PB2 4 &pcfg_pull_none>;
1542 uart5m2_xfer: uart5m2-xfer {
1545 <2 RK_PA1 3 &pcfg_pull_up>,
1547 <2 RK_PA0 3 &pcfg_pull_up>;
1549 uart5m2_ctsn: uart5m2-ctsn {
1551 <2 RK_PA3 3 &pcfg_pull_none>;
1553 uart5m2_rtsn: uart5m2-rtsn {
1555 <2 RK_PA2 3 &pcfg_pull_none>;