arm/dts/rv1108.dtsi

4  * SPDX-License-Identifier:     GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/rv1108-cru.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/media/rockchip_mipi_dsi.h>
13 #include <linux/media-bus-format.h>
15 	#address-cells = <1>;
16 	#size-cells = <1>;
20 	interrupt-parent = <&gic>;
31 		#address-cells = <1>;
32 		#size-cells = <0>;
36 			compatible = "arm,cortex-a7";
41 	arm-pmu {
42 		compatible = "arm,cortex-a7-pmu";
46 	display_subsystem: display-subsystem {
47 		compatible = "rockchip,display-subsystem";
52 			route_dsi: route-dsi {
63 	mipi_dphy: mipi-dphy@0x20228000 {
64 		compatible = "rockchip,rv1108-mipi-dphy";
66 		clock-output-names = "mipi_dphy_pll";
67 		#clock-cells = <0>;
69 		reset-names = "apb";
70 		#phy-cells = <0>;
75 		compatible = "rockchip,rv1108-mipi-dsi";
79 		clock-names = "pclk", "hs_clk";
81 		reset-names = "apb";
83 		phy-names = "mipi_dphy";
85 		#address-cells = <1>;
86 		#size-cells = <0>;
87 		pinctrl-names = "default";
88 		pinctrl-0 = <&lcdc_mipi_data>;
92 			#address-cells = <1>;
93 			#size-cells = <0>;
98 				#address-cells = <1>;
99 				#size-cells = <0>;
103 					remote-endpoint = <&vop_out_mipi>;
111 		compatible = "arm,armv7-timer";
114 		clock-frequency = <24000000>;
118 		compatible = "fixed-clock";
119 		clock-frequency = <24000000>;
120 		clock-output-names = "xin24m";
121 		#clock-cells = <0>;
125 		compatible = "simple-bus";
126 		#address-cells = <1>;
127 		#size-cells = <1>;
134 			#dma-cells = <1>;
135 			arm,pl330-broken-no-flushp;
137 			clock-names = "apb_pclk";
142 		compatible = "mmio-sram";
144 		#address-cells = <1>;
145 		#size-cells = <1>;
150 		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
153 		reg-shift = <2>;
154 		reg-io-width = <4>;
155 		clock-frequency = <24000000>;
157 		clock-names = "baudclk", "apb_pclk";
158 		pinctrl-names = "default";
159 		pinctrl-0 = <&uart2m0_xfer>;
164 		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
167 		reg-shift = <2>;
168 		reg-io-width = <4>;
169 		clock-frequency = <24000000>;
171 		clock-names = "baudclk", "apb_pclk";
172 		pinctrl-names = "default";
173 		pinctrl-0 = <&uart1_xfer>;
178 		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
181 		reg-shift = <2>;
182 		reg-io-width = <4>;
183 		clock-frequency = <24000000>;
185 		clock-names = "baudclk", "apb_pclk";
186 		pinctrl-names = "default";
187 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
192 		compatible = "rockchip,rv1108-grf", "syscon";
196 	u2phy: usb2-phy@10300100 {
197 		compatible = "rockchip,rv1108-usb2phy";
200 		#phy-cells = <1>;
203 		u2phy_otg: otg-port {
205 			interrupt-names = "otg-mux";
206 			#phy-cells = <0>;
210 		u2phy_host: host-port {
212 			interrupt-names = "linestate";
213 			#phy-cells = <0>;
219 		compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
222 		#io-channel-cells = <1>;
223 		clock-frequency = <1000000>;
225 		clock-names = "saradc", "apb_pclk";
230 		compatible = "rockchip,rk1108-pwm", "rockchip,rk3328-pwm";
233 		#pwm-cells = <3>;
234 		pinctrl-names = "active";
235 		pinctrl-0 = <&pwm0_pin>;
237 		clock-names = "pwm", "pclk";
242 		compatible = "rockchip,rv1108-pmugrf", "syscon";
246 	cru: clock-controller@20200000 {
247 		compatible = "rockchip,rv1108-cru";
250 		#clock-cells = <1>;
251 		#reset-cells = <1>;
254 		compatible = "rockchip,rv1108-i2c";
258 		#address-cells = <1>;
259 		#size-cells = <0>;
261 		clock-names = "i2c", "pclk";
262 		pinctrl-names = "default";
263 		pinctrl-0 = <&i2c0_xfer>;
267 		compatible = "rockchip,rv1108-usbgrf", "syscon";
272 		compatible = "rockchip,rk-nandc";
277 		clock-names = "clk_nandc", "hclk_nandc";
282 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
283 		clock-freq-min-max = <400000 150000000>;
286 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
287 		fifo-depth = <0x100>;
294 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
295 		clock-freq-min-max = <400000 150000000>;
298 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
299 		fifo-depth = <0x100>;
306 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
307 		clock-freq-min-max = <400000 100000000>;
310 		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
311 		cd-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
312 		fifo-depth = <0x100>;
319 		compatible = "generic-ehci";
323 		phy-names = "usb";
328 		compatible = "generic-ohci";
332 		phy-names = "usb";
337 		compatible = "rockchip,rv1108-usb", "rockchip,rk3288-usb",
341 		hnp-srp-disable;
344 		phy-names = "usb";
351 		#address-cells = <1>;
352 		#size-cells = <0>;
355 		clock-names = "clk_sfc", "hclk_sfc";
356 		pinctrl-0 = <&sfc_pins>;
357 		pinctrl-names = "default";
362 		compatible = "rockchip,rv1108-gmac";
365 		interrupt-names = "macirq";
371                 clock-names = "stmmaceth",
375 		pinctrl-names = "default";
376 		pinctrl-0 = <&rmii_pins>;
377 		phy-mode = "rmii";
378 		max-speed = <100>;
382 	gic: interrupt-controller@32010000 {
383 		compatible = "arm,gic-400";
384 		interrupt-controller;
385 		#interrupt-cells = <3>;
386 		#address-cells = <0>;
396 		compatible = "rockchip,rv1108-pinctrl";
399 		#address-cells = <1>;
400 		#size-cells = <1>;
404 			compatible = "rockchip,gpio-bank";
409 			gpio-controller;
410 			#gpio-cells = <2>;
412 			interrupt-controller;
413 			#interrupt-cells = <2>;
417 			compatible = "rockchip,gpio-bank";
422 			gpio-controller;
423 			#gpio-cells = <2>;
425 			interrupt-controller;
426 			#interrupt-cells = <2>;
430 			compatible = "rockchip,gpio-bank";
435 			gpio-controller;
436 			#gpio-cells = <2>;
438 			interrupt-controller;
439 			#interrupt-cells = <2>;
443 			compatible = "rockchip,gpio-bank";
448 			gpio-controller;
449 			#gpio-cells = <2>;
451 			interrupt-controller;
452 			#interrupt-cells = <2>;
455 		pcfg_pull_up: pcfg-pull-up {
456 			bias-pull-up;
459 		pcfg_pull_down: pcfg-pull-down {
460 			bias-pull-down;
463 		pcfg_pull_none: pcfg-pull-none {
464 			bias-disable;
467 		pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
468 			drive-strength = <8>;
471 		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
472 			drive-strength = <12>;
475 		pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
476 			bias-pull-up;
477 			drive-strength = <8>;
480 		pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
481 			drive-strength = <4>;
484 		pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
485 			bias-pull-up;
486 			drive-strength = <4>;
489 		pcfg_pull_none_smt: pcfg-pull-none-smt {
490 			bias-disable;
491 			input-schmitt-enable;
494 		pcfg_output_high: pcfg-output-high {
495 			output-high;
498 		pcfg_output_low: pcfg-output-low {
499 			output-low;
502 		pcfg_input_high: pcfg-input-high {
503 			bias-pull-up;
504 			input-enable;
508 			pwm0_pin: pwm0-pin {
514 			rmii_pins: rmii-pins {
529 			lcdc_mipi_data: lcdc-mipi_data {
546 			i2c0_xfer: i2c0-xfer {
553 			i2c1_xfer: i2c1-xfer {
560 			i2c2m1_xfer: i2c2m1-xfer {
565 			i2c2m1_gpio: i2c2m1-gpio {
572 			i2c2m05v_xfer: i2c2m05v-xfer {
577 			i2c2m05v_gpio: i2c2m05v-gpio {
584 			i2c3_xfer: i2c3-xfer {
591 			sfc_pins: sfc-pins {
602 			sdmmc_clk: sdmmc-clk {
606 			sdmmc_cmd: sdmmc-cmd {
610 			sdmmc_cd: sdmmc-cd {
614 			sdmmc_bus1: sdmmc-bus1 {
618 			sdmmc_bus4: sdmmc-bus4 {
627 			uart0_xfer: uart0-xfer {
632 			uart0_cts: uart0-cts {
636 			uart0_rts: uart0-rts {
640 			uart0_rts_gpio: uart0-rts-gpio {
646 			uart1_xfer: uart1-xfer {
651 			uart1_cts: uart1-cts {
655 			uart01rts: uart1-rts {
661 			uart2m0_xfer: uart2m0-xfer {
668 			uart2m1_xfer: uart2m1-xfer {
675 			uart2_5v_cts: uart2_5v-cts {
679 			uart2_5v_rts: uart2_5v-rts {
686                 compatible = "rockchip,rv1108-dmc";
697 		compatible = "rockchip,rv1108-vop";
699 		reg-names = "regs";
703 		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
707 			#address-cells = <1>;
708 			#size-cells = <0>;
712 				remote-endpoint = <&mipi_in_vop>;