Lines Matching +full:pwm +full:- +full:names
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include <dt-bindings/clock/rv1106-cru.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/soc/rockchip-system-status.h>
12 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
20 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a7";
64 arm-pmu {
65 compatible = "arm,cortex-a7-pmu";
67 interrupt-affinity = <&cpu0>;
72 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
73 nvmem-cell-names = "id", "cpu-version", "cpu-code";
77 csi2_dphy0: csi2-dphy0 {
78 compatible = "rockchip,rv1106-csi2-dphy";
84 csi2_dphy1: csi2-dphy1 {
85 compatible = "rockchip,rv1106-csi2-dphy";
91 csi2_dphy2: csi2-dphy2 {
92 compatible = "rockchip,rv1106-csi2-dphy";
97 display_subsystem: display-subsystem {
98 compatible = "rockchip,display-subsystem";
103 fiq_debugger: fiq-debugger {
104 compatible = "rockchip,fiq-debugger";
105 rockchip,serial-id = <2>;
106 rockchip,wake-irq = <0>;
107 rockchip,irq-mode-enable = <0>;
113 mpp_srv: mpp-srv {
114 compatible = "rockchip,mpp-service";
115 rockchip,taskqueue-count = <2>;
119 mpp_vcodec: mpp-vcodec {
124 reserved-memory {
125 #address-cells = <1>;
126 #size-cells = <1>;
130 compatible = "shared-dma-pool";
134 linux,cma-default;
138 rkcif_dvp: rkcif-dvp {
139 compatible = "rockchip,rkcif-dvp";
144 rkcif_dvp_sditf: rkcif-dvp-sditf {
145 compatible = "rockchip,rkcif-sditf";
150 rkcif_mipi_lvds: rkcif-mipi-lvds {
151 compatible = "rockchip,rkcif-mipi-lvds";
156 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
157 compatible = "rockchip,rkcif-sditf";
162 rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
163 compatible = "rockchip,rkcif-mipi-lvds";
168 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
169 compatible = "rockchip,rkcif-sditf";
174 rkisp_vir0: rkisp-vir0 {
175 compatible = "rockchip,rkisp-vir";
181 rkisp_vir1: rkisp-vir1 {
182 compatible = "rockchip,rkisp-vir";
187 rkisp_vir2: rkisp-vir2 {
188 compatible = "rockchip,rkisp-vir";
193 rkisp_vir3: rkisp-vir3 {
194 compatible = "rockchip,rkisp-vir";
199 rockchip_system_monitor: rockchip-system-monitor {
200 compatible = "rockchip,system-monitor";
202 rockchip,thermal-zone = "soc-thermal";
205 thermal_zones: thermal-zones {
206 soc_thermal: soc-thermal {
207 polling-delay-passive = <20>; /* milliseconds */
208 polling-delay = <1000>; /* milliseconds */
209 sustainable-power = <2100>; /* milliwatts */
211 thermal-sensors = <&tsadc 0>;
213 threshold: trip-point-0 {
218 target: trip-point-1 {
223 soc_crit: soc-crit {
235 compatible = "arm,armv7-timer";
237 clock-frequency = <24000000>;
241 compatible = "fixed-clock";
242 clock-frequency = <24000000>;
243 clock-output-names = "xin24m";
244 #clock-cells = <0>;
248 compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd";
251 grf_cru: grf-clock-controller {
252 compatible = "rockchip,rv1106-grf-cru";
253 #clock-cells = <1>;
256 reboot_mode: reboot-mode {
257 compatible = "syscon-reboot-mode";
259 mode-bootloader = <BOOT_BL_DOWNLOAD>;
260 mode-charge = <BOOT_CHARGING>;
261 mode-fastboot = <BOOT_FASTBOOT>;
262 mode-loader = <BOOT_BL_DOWNLOAD>;
263 mode-normal = <BOOT_NORMAL>;
264 mode-recovery = <BOOT_RECOVERY>;
265 mode-ums = <BOOT_UMS>;
266 mode-panic = <BOOT_PANIC>;
267 mode-watchdog = <BOOT_WATCHDOG>;
271 compatible = "rockchip,rv1106-rgb";
275 #address-cells = <1>;
276 #size-cells = <0>;
280 #address-cells = <1>;
281 #size-cells = <0>;
285 remote-endpoint = <&vop_out_rgb>;
293 compatible = "rockchip,rtc-1.0";
298 clock-names = "pclk_phy", "pclk_test";
299 assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
300 assigned-clock-rates = <24000000>;
304 gic: interrupt-controller@ff1f0000 {
305 compatible = "arm,gic-400";
306 interrupt-controller;
307 #interrupt-cells = <3>;
308 #address-cells = <0>;
317 arm-debug@ff200000 {
323 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
326 #address-cells = <1>;
327 #size-cells = <0>;
329 clock-names = "i2c", "pclk";
330 pinctrl-names = "default";
331 pinctrl-0 = <&i2c0m0_xfer>;
336 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
339 #address-cells = <1>;
340 #size-cells = <0>;
342 clock-names = "i2c", "pclk";
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c1m0_xfer>;
348 dsm: codec-digital@ff340000 {
349 compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1";
352 clock-names = "dac", "pclk";
354 reset-names = "reset" ;
356 rockchip,pwm-output-mode;
357 #sound-dai-cells = <0>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&dsmaudio_pins>;
363 pwm0: pwm@ff350000 {
364 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
366 #pwm-cells = <3>;
367 pinctrl-names = "active";
368 pinctrl-0 = <&pwm0m0_pins>;
370 clock-names = "pwm", "pclk";
374 pwm1: pwm@ff350010 {
375 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
377 #pwm-cells = <3>;
378 pinctrl-names = "active";
379 pinctrl-0 = <&pwm1m0_pins>;
381 clock-names = "pwm", "pclk";
385 pwm2: pwm@ff350020 {
386 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
388 #pwm-cells = <3>;
389 pinctrl-names = "active";
390 pinctrl-0 = <&pwm2m0_pins>;
392 clock-names = "pwm", "pclk";
396 pwm3: pwm@ff350030 {
397 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
401 #pwm-cells = <3>;
402 pinctrl-names = "active";
403 pinctrl-0 = <&pwm3m0_pins>;
405 clock-names = "pwm", "pclk";
409 pwm4: pwm@ff360000 {
410 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
412 #pwm-cells = <3>;
413 pinctrl-names = "active";
414 pinctrl-0 = <&pwm4m0_pins>;
416 clock-names = "pwm", "pclk";
420 pwm5: pwm@ff360010 {
421 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
423 #pwm-cells = <3>;
424 pinctrl-names = "active";
425 pinctrl-0 = <&pwm5m0_pins>;
427 clock-names = "pwm", "pclk";
431 pwm6: pwm@ff360020 {
432 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
434 #pwm-cells = <3>;
435 pinctrl-names = "active";
436 pinctrl-0 = <&pwm6m0_pins>;
438 clock-names = "pwm", "pclk";
442 pwm7: pwm@ff360030 {
443 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
447 #pwm-cells = <3>;
448 pinctrl-names = "active";
449 pinctrl-0 = <&pwm7m0_pins>;
451 clock-names = "pwm", "pclk";
456 compatible = "rockchip,rv1106-mailbox",
457 "rockchip,rk3368-mailbox";
461 clock-names = "pclk_mailbox";
462 #mbox-cells = <1>;
467 compatible = "rockchip,rv1106-pmuioc", "syscon";
471 cru: clock-controller@ff3a0000 {
472 compatible = "rockchip,rv1106-cru";
475 #clock-cells = <1>;
476 #reset-cells = <1>;
478 assigned-clocks =
485 assigned-clock-rates =
495 compatible = "rockchip,rv1106-saradc";
498 #io-channel-cells = <1>;
500 clock-names = "saradc", "apb_pclk";
502 reset-names = "saradc-apb";
507 compatible = "rockchip,rv1106-tsadc";
512 clock-names = "tsadc", "apb_pclk", "tsen";
513 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
514 assigned-clock-rates = <1000000>, <12000000>;
516 reset-names = "tsadc", "tsadc-apb";
517 #thermal-sensor-cells = <1>;
518 rockchip,hw-tshut-temp = <120000>;
519 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
520 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
525 compatible = "rockchip,rv1106-otp";
527 #address-cells = <1>;
528 #size-cells = <1>;
532 clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
536 reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
539 cpu_code: cpu-code@2 {
542 otp_cpu_version: cpu-version@8 {
549 cpu_leakage: cpu-leakage@1a {
552 log_leakage: log-leakage@1b {
555 macphy_bgs: macphy-bgs@2d {
558 macphy_txlevel: macphy-txlevel@2e {
563 u2phy: usb2-phy@ff3e0000 {
564 compatible = "rockchip,rv1106-usb2phy";
568 clock-names = "phyclk", "pclk";
570 reset-names = "u2phy", "u2phy-apb";
571 #clock-cells = <0>;
574 u2phy_otg: otg-port {
575 #phy-cells = <0>;
580 interrupt-names = "otg-bvalid", "otg-id",
586 csi2_dphy_hw: csi2-dphy-hw@ff3e8000 {
587 compatible = "rockchip,rv1106-csi2-dphy-hw";
590 clock-names = "pclk";
592 reset-names = "srst_p_csiphy";
597 dmac: dma-controller@ff420000 {
609 #dma-cells = <1>;
611 clock-names = "apb_pclk";
612 arm,pl330-periph-burst;
616 compatible = "rockchip,crypto-v3";
621 clock-names = "aclk", "hclk", "sclk", "pka";
622 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
623 assigned-clock-rates = <300000000>, <300000000>;
625 reset-names = "crypto-rst";
634 clock-names = "hclk_trng";
636 reset-names = "reset";
641 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
644 #address-cells = <1>;
645 #size-cells = <0>;
647 clock-names = "i2c", "pclk";
648 pinctrl-names = "default";
649 pinctrl-0 = <&i2c2m0_xfer>;
654 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
657 #address-cells = <1>;
658 #size-cells = <0>;
660 clock-names = "i2c", "pclk";
661 pinctrl-names = "default";
662 pinctrl-0 = <&i2c3m0_xfer>;
667 compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
670 #address-cells = <1>;
671 #size-cells = <0>;
673 clock-names = "i2c", "pclk";
674 pinctrl-names = "default";
675 pinctrl-0 = <&i2c4m0_xfer>;
679 pwm8: pwm@ff490000 {
680 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
682 #pwm-cells = <3>;
683 pinctrl-names = "active";
684 pinctrl-0 = <&pwm8m0_pins>;
686 clock-names = "pwm", "pclk";
690 pwm9: pwm@ff490010 {
691 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
693 #pwm-cells = <3>;
694 pinctrl-names = "active";
695 pinctrl-0 = <&pwm9m0_pins>;
697 clock-names = "pwm", "pclk";
701 pwm10: pwm@ff490020 {
702 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
704 #pwm-cells = <3>;
705 pinctrl-names = "active";
706 pinctrl-0 = <&pwm10m0_pins>;
708 clock-names = "pwm", "pclk";
712 pwm11: pwm@ff490030 {
713 compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
717 #pwm-cells = <3>;
718 pinctrl-names = "active";
719 pinctrl-0 = <&pwm11m0_pins>;
721 clock-names = "pwm", "pclk";
726 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
729 reg-shift = <2>;
730 reg-io-width = <4>;
732 clock-frequency = <24000000>;
734 clock-names = "baudclk", "apb_pclk";
735 pinctrl-names = "default";
736 pinctrl-0 = <&uart0m0_xfer>;
741 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
744 reg-shift = <2>;
745 reg-io-width = <4>;
747 clock-frequency = <24000000>;
749 clock-names = "baudclk", "apb_pclk";
750 pinctrl-names = "default";
751 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
756 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
759 reg-shift = <2>;
760 reg-io-width = <4>;
762 clock-frequency = <24000000>;
764 clock-names = "baudclk", "apb_pclk";
765 pinctrl-names = "default";
766 pinctrl-0 = <&uart2m1_xfer>;
771 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
774 reg-shift = <2>;
775 reg-io-width = <4>;
777 clock-frequency = <24000000>;
779 clock-names = "baudclk", "apb_pclk";
780 pinctrl-names = "default";
781 pinctrl-0 = <&uart3m0_xfer>;
786 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
789 reg-shift = <2>;
790 reg-io-width = <4>;
792 clock-frequency = <24000000>;
794 clock-names = "baudclk", "apb_pclk";
795 pinctrl-names = "default";
796 pinctrl-0 = <&uart4m0_xfer>;
801 compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
804 reg-shift = <2>;
805 reg-io-width = <4>;
807 clock-frequency = <24000000>;
809 clock-names = "baudclk", "apb_pclk";
810 pinctrl-names = "default";
811 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
816 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
819 #address-cells = <1>;
820 #size-cells = <0>;
822 clock-names = "spiclk", "apb_pclk";
824 dma-names = "tx", "rx";
825 pinctrl-names = "default";
826 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
831 compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
834 #address-cells = <1>;
835 #size-cells = <0>;
837 clock-names = "spiclk", "apb_pclk";
839 dma-names = "tx", "rx";
840 pinctrl-names = "default";
841 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
846 compatible = "rockchip,hw-decompress";
850 clock-names = "aclk", "dclk", "pclk";
852 reset-names = "dresetn";
857 compatible = "rockchip,rv1106-ioc", "syscon";
862 compatible = "rockchip,rv1106-wdt", "snps,dw-wdt";
870 compatible = "rockchip,rv1106-mailbox",
871 "rockchip,rk3368-mailbox";
875 clock-names = "pclk_mailbox";
876 #mbox-cells = <1>;
881 compatible = "rockchip,rv1106-rknpu";
885 clock-names = "aclk", "hclk";
887 reset-names = "srst_a", "srst_h";
896 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
901 compatible = "rockchip,rv1106-vop";
903 reg-names = "regs";
907 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
911 #address-cells = <1>;
912 #size-cells = <0>;
916 remote-endpoint = <&rgb_in_vop>;
922 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
927 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
928 fifo-depth = <0x100>;
929 max-frequency = <200000000>;
934 compatible = "rockchip,rv1106-rkisp";
939 interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
942 clock-names = "aclk_isp", "hclk_isp",
948 compatible = "rockchip,rv1106-cif";
950 reg-names = "cif_regs";
952 interrupt-names = "cif-intr";
959 clock-names = "aclk_cif","hclk_cif",
970 reset-names = "rst_cif_a","rst_cif_h",
979 mipi0_csi2: mipi-csi2@ffa20000 {
980 compatible = "rockchip,rk3588-mipi-csi2";
982 reg-names = "csihost_regs";
985 interrupt-names = "csi-intr1", "csi-intr2";
987 clock-names = "pclk_csi2host", "clk_rxbyte_hs";
989 reset-names = "srst_csihost_p";
993 mipi1_csi2: mipi-csi2@ffa30000 {
994 compatible = "rockchip,rk3588-mipi-csi2";
996 reg-names = "csihost_regs";
999 interrupt-names = "csi-intr1", "csi-intr2";
1001 clock-names = "pclk_csi2host", "clk_rxbyte_hs";
1003 reset-names = "srst_csihost_p";
1008 compatible = "rockchip,rkv-encoder-rv1106";
1011 interrupt-names = "irq_rkvenc";
1013 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
1014 rockchip,normal-rates = <300000000>, <0>, <400000000>;
1015 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>;
1016 assigned-clock-rates = <300000000>, <400000000>;
1018 reset-names = "video_a", "video_h", "video_core";
1020 rockchip,taskqueue-node = <0>;
1026 compatible = "rockchip,rk-dvbm";
1029 interrupt-names = "irq_rkdvbm";
1031 clock-names = "clk_core";
1032 assigned-clocks = <&cru CLK_CORE_VEPU_DVBM>;
1033 assigned-clock-rates = <200000000>;
1035 reset-names = "dvbm_rst";
1040 compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a";
1044 interrupt-names = "macirq", "eth_wake_irq";
1048 clock-names = "stmmaceth", "clk_mac_ref",
1051 reset-names = "stmmaceth";
1053 snps,mixed-burst;
1056 tx-dma-size = <256>;
1057 rx-dma-size = <16>;
1059 snps,axi-config = <&stmmac_axi_setup>;
1060 snps,mtl-rx-config = <&mtl_rx_setup>;
1061 snps,mtl-tx-config = <&mtl_tx_setup>;
1063 phy-mode = "rmii";
1065 phy-handle = <&rmii_phy>;
1067 nvmem-cells = <&macphy_bgs>;
1068 nvmem-cell-names = "bgs";
1072 compatible = "snps,dwmac-mdio";
1073 #address-cells = <0x1>;
1074 #size-cells = <0x0>;
1075 rmii_phy: ethernet-phy@2 {
1076 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
1080 phy-is-integrated;
1081 nvmem-cells = <&macphy_txlevel>;
1082 nvmem-cell-names = "txlevel";
1086 stmmac_axi_setup: stmmac-axi-config {
1092 mtl_rx_setup: rx-queues-config {
1093 snps,rx-queues-to-use = <1>;
1099 mtl_tx_setup: tx-queues-config {
1100 snps,tx-queues-to-use = <1>;
1108 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
1113 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1114 fifo-depth = <0x100>;
1115 max-frequency = <200000000>;
1116 rockchip,use-v2-tuning;
1121 compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
1126 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1127 cd-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
1128 fifo-depth = <0x100>;
1129 max-frequency = <200000000>;
1130 pinctrl-names = "default";
1131 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
1140 clock-names = "clk_sfc", "hclk_sfc";
1141 assigned-clocks = <&cru SCLK_SFC>;
1142 assigned-clock-rates = <75000000>;
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1153 clock-names = "aclk_rve", "hclk_rve";
1158 compatible = "rockchip,rv1106-i2s-tdm";
1162 clock-names = "mclk_tx", "mclk_rx", "hclk";
1164 dma-names = "tx", "rx";
1166 reset-names = "tx-m", "rx-m";
1167 rockchip,clk-trcm = <1>;
1168 #sound-dai-cells = <0>;
1173 compatible = "rockchip,rv1106-dwc3", "rockchip,rk3399-dwc3";
1176 clock-names = "ref", "utmi", "bus";
1177 #address-cells = <1>;
1178 #size-cells = <1>;
1187 reset-names = "usb3-otg";
1189 maximum-speed = "high-speed";
1191 phy-names = "usb2-phy";
1194 snps,dis-u2-freeclk-exists-quirk;
1196 snps,dis-del-phy-power-chg-quirk;
1197 snps,dis-tx-ipgap-linecheck-quirk;
1203 compatible = "rockchip,rv1106-pinctrl";
1206 #address-cells = <1>;
1207 #size-cells = <1>;
1211 compatible = "rockchip,gpio-bank";
1216 gpio-controller;
1217 #gpio-cells = <2>;
1218 gpio-ranges = <&pinctrl 0 0 32>;
1219 interrupt-controller;
1220 #interrupt-cells = <2>;
1224 compatible = "rockchip,gpio-bank";
1229 gpio-controller;
1230 #gpio-cells = <2>;
1231 gpio-ranges = <&pinctrl 0 32 32>;
1232 interrupt-controller;
1233 #interrupt-cells = <2>;
1237 compatible = "rockchip,gpio-bank";
1242 gpio-controller;
1243 #gpio-cells = <2>;
1244 gpio-ranges = <&pinctrl 0 64 32>;
1245 interrupt-controller;
1246 #interrupt-cells = <2>;
1250 compatible = "rockchip,gpio-bank";
1255 gpio-controller;
1256 #gpio-cells = <2>;
1257 gpio-ranges = <&pinctrl 0 96 32>;
1258 interrupt-controller;
1259 #interrupt-cells = <2>;
1263 compatible = "rockchip,gpio-bank";
1268 gpio-controller;
1269 #gpio-cells = <2>;
1270 gpio-ranges = <&pinctrl 0 128 32>;
1271 interrupt-controller;
1272 #interrupt-cells = <2>;
1277 #include "rv1106-pinctrl.dtsi"