Lines Matching +full:0 +full:xff3a0000
55 #size-cells = <0>;
60 reg = <0xf00>;
106 rockchip,wake-irq = <0>;
107 rockchip,irq-mode-enable = <0>;
133 size = <0x800000>;
211 thermal-sensors = <&tsadc 0>;
213 threshold: trip-point-0 {
244 #clock-cells = <0>;
249 reg = <0xff000000 0x68000>;
258 offset = <0x20200>;
276 #size-cells = <0>;
278 port@0 {
279 reg = <0>;
281 #size-cells = <0>;
283 rgb_in_vop: endpoint@0 {
284 reg = <0>;
294 reg = <0xff1c0000 0x1000>;
308 #address-cells = <0>;
310 reg = <0xff1f1000 0x1000>,
311 <0xff1f2000 0x2000>,
312 <0xff1f4000 0x2000>,
313 <0xff1f6000 0x2000>;
319 reg = <0xff200000 0x1000>;
324 reg = <0xff310000 0x1000>;
327 #size-cells = <0>;
331 pinctrl-0 = <&i2c0m0_xfer>;
337 reg = <0xff320000 0x1000>;
340 #size-cells = <0>;
344 pinctrl-0 = <&i2c1m0_xfer>;
350 reg = <0xff340000 0x1000>;
357 #sound-dai-cells = <0>;
359 pinctrl-0 = <&dsmaudio_pins>;
365 reg = <0xff350000 0x10>;
368 pinctrl-0 = <&pwm0m0_pins>;
376 reg = <0xff350010 0x10>;
379 pinctrl-0 = <&pwm1m0_pins>;
387 reg = <0xff350020 0x10>;
390 pinctrl-0 = <&pwm2m0_pins>;
398 reg = <0xff350030 0x10>;
403 pinctrl-0 = <&pwm3m0_pins>;
411 reg = <0xff360000 0x10>;
414 pinctrl-0 = <&pwm4m0_pins>;
422 reg = <0xff360010 0x10>;
425 pinctrl-0 = <&pwm5m0_pins>;
433 reg = <0xff360020 0x10>;
436 pinctrl-0 = <&pwm6m0_pins>;
444 reg = <0xff360030 0x10>;
449 pinctrl-0 = <&pwm7m0_pins>;
458 reg = <0xff378000 0x200>;
468 reg = <0xff388000 0x1000>;
473 reg = <0xff3a0000 0x20000>;
496 reg = <0xff3c0000 0x100>;
508 reg = <0xff3c8000 0x1000>;
519 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
520 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
526 reg = <0xff3d0000 0x4000>;
540 reg = <0x02 0x2>;
543 reg = <0x08 0x1>;
547 reg = <0x0a 0x10>;
550 reg = <0x1a 0x1>;
553 reg = <0x1b 0x1>;
556 reg = <0x2d 0x1>;
559 reg = <0x2e 0x2>;
565 reg = <0xff3e0000 0x8000>;
571 #clock-cells = <0>;
575 #phy-cells = <0>;
588 reg = <0xff3e8000 0x8000>;
599 reg = <0xff420000 0x4000>;
617 reg = <0xff440000 0x2000>;
631 reg = <0xff448000 0x200>;
642 reg = <0xff450000 0x1000>;
645 #size-cells = <0>;
649 pinctrl-0 = <&i2c2m0_xfer>;
655 reg = <0xff460000 0x1000>;
658 #size-cells = <0>;
662 pinctrl-0 = <&i2c3m0_xfer>;
668 reg = <0xff470000 0x1000>;
671 #size-cells = <0>;
675 pinctrl-0 = <&i2c4m0_xfer>;
681 reg = <0xff490000 0x10>;
684 pinctrl-0 = <&pwm8m0_pins>;
692 reg = <0xff490010 0x10>;
695 pinctrl-0 = <&pwm9m0_pins>;
703 reg = <0xff490020 0x10>;
706 pinctrl-0 = <&pwm10m0_pins>;
714 reg = <0xff490030 0x10>;
719 pinctrl-0 = <&pwm11m0_pins>;
727 reg = <0xff4a0000 0x100>;
736 pinctrl-0 = <&uart0m0_xfer>;
742 reg = <0xff4b0000 0x100>;
751 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
757 reg = <0xff4c0000 0x100>;
766 pinctrl-0 = <&uart2m1_xfer>;
772 reg = <0xff4d0000 0x100>;
781 pinctrl-0 = <&uart3m0_xfer>;
787 reg = <0xff4e0000 0x100>;
796 pinctrl-0 = <&uart4m0_xfer>;
802 reg = <0xff4f0000 0x100>;
811 pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
817 reg = <0xff500000 0x1000>;
820 #size-cells = <0>;
823 dmas = <&dmac 1>, <&dmac 0>;
826 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
832 reg = <0xff510000 0x1000>;
835 #size-cells = <0>;
841 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
847 reg = <0xff520000 0x1000>;
858 reg = <0xff538000 0x40000>;
863 reg = <0xff5a0000 0x100>;
872 reg = <0xff5c0000 0x200>;
882 reg = <0xff660000 0x10000>;
893 reg = <0xff980000 0x1000>;
902 reg = <0xff990000 0x200>;
912 #size-cells = <0>;
914 vop_out_rgb: endpoint@0 {
915 reg = <0>;
923 reg = <0xff9a0000 0x4000>;
928 fifo-depth = <0x100>;
935 reg = <0xffa00000 0x7f00>;
949 reg = <0xffa10000 0x10000>;
981 reg = <0xffa20000 0x10000>;
995 reg = <0xffa30000 0x10000>;
1009 reg = <0xffa50000 0x6000>;
1014 rockchip,normal-rates = <300000000>, <0>, <400000000>;
1020 rockchip,taskqueue-node = <0>;
1027 reg = <0xffa70000 0x90>;
1041 reg = <0xffa80000 0x10000>;
1073 #address-cells = <0x1>;
1074 #size-cells = <0x0>;
1089 snps,blen = <0 0 0 0 16 8 4>;
1109 reg = <0xffa90000 0x4000>;
1114 fifo-depth = <0x100>;
1122 reg = <0xffaa0000 0x4000>;
1128 fifo-depth = <0x100>;
1131 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
1137 reg = <0xffac0000 0x4000>;
1144 #size-cells = <0>;
1150 reg = <0xffad0000 0x1000>;
1159 reg = <0xffae0000 0x1000>;
1168 #sound-dai-cells = <0>;
1184 reg = <0xffb00000 0x100000>;
1212 reg = <0xff380000 0x100>;
1218 gpio-ranges = <&pinctrl 0 0 32>;
1225 reg = <0xff530000 0x100>;
1231 gpio-ranges = <&pinctrl 0 32 32>;
1238 reg = <0xff540000 0x100>;
1244 gpio-ranges = <&pinctrl 0 64 32>;
1251 reg = <0xff550000 0x100>;
1257 gpio-ranges = <&pinctrl 0 96 32>;
1264 reg = <0xff560000 0x100>;
1270 gpio-ranges = <&pinctrl 0 128 32>;