Lines Matching +full:rv1106 +full:- +full:cru
4 * SPDX-License-Identifier: GPL-2.0+
14 stdout-path = &uart2;
15 u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
18 secure-otp@ff3fd8000 {
19 compatible = "rockchip,rv1106-secure-otp";
24 u-boot,dm-spl;
30 mmc-ecsd = <0x3F000>;
31 bus-width = <8>;
32 mmc-hs200-1_8v;
33 u-boot,dm-spl;
37 &cru {
38 u-boot,dm-spl;
43 u-boot,dm-spl;
48 u-boot,dm-spl;
53 u-boot,dm-spl;
58 u-boot,dm-spl;
63 u-boot,dm-spl;
68 u-boot,dm-spl;
73 u-boot,dm-spl;
77 u-boot,dm-spl;
81 u-boot,dm-spl;
85 u-boot,dm-spl;
89 u-boot,dm-spl;
93 u-boot,dm-spl;
98 u-boot,dm-spl;
103 u-boot,dm-spl;
108 u-boot,dm-spl;
112 u-boot,dm-spl;
116 u-boot,dm-pre-reloc;
121 u-boot,dm-pre-reloc;
126 u-boot,dm-pre-reloc;
131 u-boot,dm-spl;
136 u-boot,dm-pre-reloc;
141 u-boot,dm-spl;
142 clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
143 clock-frequency = <300000000>, <300000000>;
148 u-boot,dm-spl;
153 u-boot,dm-pre-reloc;
158 u-boot,dm-spl;
161 #address-cells = <1>;
162 #size-cells = <0>;
164 u-boot,dm-spl;
165 compatible = "spi-nand";
167 spi-tx-bus-width = <1>;
168 spi-rx-bus-width = <4>;
169 spi-max-frequency = <80000000>;
173 u-boot,dm-spl;
174 compatible = "jedec,spi-nor";
177 spi-tx-bus-width = <1>;
178 spi-rx-bus-width = <4>;
179 spi-max-frequency = <100000000>;
184 u-boot,dm-pre-reloc;
189 u-boot,dm-pre-reloc;
194 u-boot,dm-pre-reloc;
199 u-boot,dm-pre-reloc;