arm/dts/rk3xxx.dtsi

5  * SPDX-License-Identifier:     GPL-2.0+ or X11
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&gic>;
34 		compatible = "simple-bus";
35 		#address-cells = <1>;
36 		#size-cells = <1>;
39 		dmac1_s: dma-controller@20018000 {
44 			#dma-cells = <1>;
45 			arm,pl330-broken-no-flushp;
47 			clock-names = "apb_pclk";
50 		dmac1_ns: dma-controller@2001c000 {
55 			#dma-cells = <1>;
56 			arm,pl330-broken-no-flushp;
58 			clock-names = "apb_pclk";
62 		dmac2: dma-controller@20078000 {
67 			#dma-cells = <1>;
68 			arm,pl330-broken-no-flushp;
70 			clock-names = "apb_pclk";
75 		compatible = "fixed-clock";
76 		clock-frequency = <24000000>;
77 		#clock-cells = <0>;
78 		clock-output-names = "xin24m";
81 	L2: l2-cache-controller@10138000 {
82 		compatible = "arm,pl310-cache";
84 		cache-unified;
85 		cache-level = <2>;
89 		compatible = "arm,cortex-a9-scu";
93 	global_timer: global-timer@1013c200 {
94 		compatible = "arm,cortex-a9-global-timer";
100 	local_timer: local-timer@1013c600 {
101 		compatible = "arm,cortex-a9-twd-timer";
107 	gic: interrupt-controller@1013d000 {
108 		compatible = "arm,cortex-a9-gic";
109 		interrupt-controller;
110 		#interrupt-cells = <3>;
116 		compatible = "snps,dw-apb-uart";
119 		reg-shift = <2>;
120 		reg-io-width = <1>;
121 		clock-names = "baudclk", "apb_pclk";
127 		compatible = "snps,dw-apb-uart";
130 		reg-shift = <2>;
131 		reg-io-width = <1>;
132 		clock-names = "baudclk", "apb_pclk";
138 		u-boot,dm-pre-reloc;
139 		compatible = "rockchip,rk3188-noc", "syscon";
144 		compatible = "rockchip,rk3066-usb", "snps,dwc2";
148 		clock-names = "otg";
150 		g-np-tx-fifo-size = <16>;
151 		g-rx-fifo-size = <275>;
152 		g-tx-fifo-size = <256 128 128 64 64 32>;
153 		g-use-dma;
155 		phy-names = "usb2-phy";
164 		clock-names = "otg";
167 		phy-names = "usb2-phy";
172 		compatible = "snps,arc-emac";
175 		#address-cells = <1>;
176 		#size-cells = <0>;
181 		clock-names = "hclk", "macref";
182 		max-speed = <100>;
183 		phy-mode = "rmii";
189 		compatible = "rockchip,rk2928-dw-mshc";
191 		max-frequency = <37500000>;
194 		clock-names = "biu", "ciu";
195 		fifo-depth = <256>;
200 		compatible = "rockchip,rk2928-dw-mshc";
202 		max-frequency = <37500000>;
205 		clock-names = "biu", "ciu";
206 		fifo-depth = <256>;
211 		compatible = "rockchip,rk2928-dw-mshc";
213 		max-frequency = <37500000>;
216 		clock-names = "biu", "ciu";
217 		fifo-depth = <256>;
222 		compatible = "rockchip,rk3066-pmu", "syscon";
224 		u-boot,dm-pre-reloc;
230 		u-boot,dm-pre-reloc;
234 		/* unreviewed u-boot-specific binding */
235 		compatible = "rockchip,rk3188-dmc", "syscon";
243 		clock-names = "pclk_ddrupctl", "pclk_publ";
244 		u-boot,dm-pre-reloc;
248 		compatible = "rockchip,rk3066-i2c";
251 		#address-cells = <1>;
252 		#size-cells = <0>;
256 		clock-names = "i2c";
263 		compatible = "rockchip,rk3066-i2c";
266 		#address-cells = <1>;
267 		#size-cells = <0>;
272 		clock-names = "i2c";
278 		compatible = "rockchip,rk2928-pwm";
280 		#pwm-cells = <2>;
286 		compatible = "rockchip,rk2928-pwm";
288 		#pwm-cells = <2>;
294 		compatible = "snps,dw-wdt";
302 		compatible = "rockchip,rk2928-pwm";
304 		#pwm-cells = <2>;
310 		compatible = "rockchip,rk2928-pwm";
312 		#pwm-cells = <2>;
318 		compatible = "rockchip,rk3066-i2c";
321 		#address-cells = <1>;
322 		#size-cells = <0>;
327 		clock-names = "i2c";
333 		compatible = "rockchip,rk3066-i2c";
336 		#address-cells = <1>;
337 		#size-cells = <0>;
342 		clock-names = "i2c";
348 		compatible = "rockchip,rk3066-i2c";
351 		#address-cells = <1>;
352 		#size-cells = <0>;
357 		clock-names = "i2c";
363 		compatible = "snps,dw-apb-uart";
366 		reg-shift = <2>;
367 		reg-io-width = <1>;
368 		clock-frequency = <24000000>;
369 		clock-names = "baudclk", "apb_pclk";
375 		compatible = "snps,dw-apb-uart";
378 		reg-shift = <2>;
379 		reg-io-width = <1>;
380 		clock-names = "baudclk", "apb_pclk";
389 		#io-channel-cells = <1>;
391 		clock-names = "saradc", "apb_pclk";
396 		compatible = "rockchip,rk3066-spi";
398 		clock-names = "spiclk", "apb_pclk";
401 		#address-cells = <1>;
402 		#size-cells = <0>;
404 		dma-names = "tx", "rx";
409 		compatible = "rockchip,rk3066-spi";
411 		clock-names = "spiclk", "apb_pclk";
414 		#address-cells = <1>;
415 		#size-cells = <0>;
417 		dma-names = "tx", "rx";