Lines Matching +full:0 +full:xfea80000
56 #size-cells = <0>;
91 cpu_l0: cpu@0 {
94 reg = <0x0>;
102 reg = <0x100>;
110 reg = <0x200>;
118 reg = <0x300>;
126 reg = <0x400>;
134 reg = <0x500>;
142 reg = <0x600>;
150 reg = <0x700>;
172 arm,smc-id = <0x82000010>;
174 #size-cells = <0>;
177 reg = <0x14>;
185 reg = <0x16>;
203 #clock-cells = <0>;
218 #clock-cells = <0>;
225 #clock-cells = <0>;
232 reg = <0x0 0x0010f000 0x0 0x100>;
235 ranges = <0 0x0 0x0010f000 0x100>;
237 scmi_shmem: scmi_shmem@0 {
239 reg = <0x0 0x100>;
255 reg = <0x0 0xfc000000 0x0 0x400000>;
276 reg = <0x0 0xfc800000 0x0 0x40000>;
288 reg = <0x0 0xfc840000 0x0 0x40000>;
300 reg = <0x0 0xfc880000 0x0 0x40000>;
312 reg = <0x0 0xfc8c0000 0x0 0x40000>;
324 reg = <0x0 0xfc900000 0x0 0x200000>;
336 reg = <0x0 0xfcb00000 0x0 0x200000>;
358 reg = <0x0 0xfcd00000 0x0 0x400000>;
375 reg = <0x0 0xfd58c000 0x0 0x1000>;
380 reg = <0x0 0xfd5a6000 0x0 0x2000>;
385 reg = <0x0 0xfd5a8000 0x0 0x100>;
390 reg = <0x0 0xfd5ac000 0x0 0x4000>;
395 reg = <0x0 0xfd5b0000 0x0 0x1000>;
400 reg = <0x0 0xfd5bc000 0x0 0x100>;
405 reg = <0x0 0xfd5c4000 0x0 0x100>;
410 reg = <0x0 0xfd5c8000 0x0 0x4000>;
416 reg = <0x0 0xfd5d0000 0x0 0x4000>;
420 u2phy0: usb2-phy@0 {
422 reg = <0x0 0x10>;
428 #clock-cells = <0>;
432 #phy-cells = <0>;
441 reg = <0x0 0xfd5d8000 0x0 0x4000>;
447 reg = <0x8000 0x10>;
453 #clock-cells = <0>;
457 #phy-cells = <0>;
466 reg = <0x0 0xfd5dc000 0x0 0x4000>;
472 reg = <0xc000 0x10>;
478 #clock-cells = <0>;
482 #phy-cells = <0>;
490 reg = <0x0 0xfd5e0000 0x0 0x100>;
495 reg = <0x0 0xfd5f0000 0x0 0x10000>;
500 reg = <0x0 0xfd600000 0x0 0x100000>;
504 ranges = <0x0 0x0 0xfd600000 0x100000>;
510 reg = <0x0 0xfd7c0000 0x0 0x5c000>;
536 reg = <0x0 0xfd880000 0x0 0x1000>;
541 pinctrl-0 = <&i2c0m0_xfer>;
543 #size-cells = <0>;
549 reg = <0x0 0xfd890000 0x0 0x100>;
557 pinctrl-0 = <&uart0m0_xfer>;
563 reg = <0x0 0xfd8b0000 0x0 0x10>;
566 pinctrl-0 = <&pwm0m0_pins>;
574 reg = <0x0 0xfd8b0010 0x0 0x10>;
577 pinctrl-0 = <&pwm1m0_pins>;
585 reg = <0x0 0xfd8b0020 0x0 0x10>;
588 pinctrl-0 = <&pwm2m0_pins>;
596 reg = <0x0 0xfd8b0030 0x0 0x10>;
601 pinctrl-0 = <&pwm3m0_pins>;
609 reg = <0x0 0xfd8d8000 0x0 0x400>;
615 #size-cells = <0>;
622 #size-cells = <0>;
627 #size-cells = <0>;
645 #size-cells = <0>;
656 #size-cells = <0>;
667 #size-cells = <0>;
688 #size-cells = <0>;
706 #size-cells = <0>;
718 #size-cells = <0>;
738 reg = <0x0 0xfda40000 0x0 0x100>;
740 #size-cells = <0>;
741 pvtm@0 {
742 reg = <0>;
750 reg = <0x0 0xfda50000 0x0 0x100>;
752 #size-cells = <0>;
762 reg = <0x0 0xfda60000 0x0 0x100>;
764 #size-cells = <0>;
774 reg = <0x0 0xfdaf0000 0x0 0x100>;
776 #size-cells = <0>;
788 reg = <0x0 0xfdb30000 0x0 0x100>;
790 #size-cells = <0>;
802 reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>;
808 #iommu-cells = <0>;
814 reg = <0x0 0xfdaca000 0x0 0x100>;
820 #iommu-cells = <0>;
826 reg = <0x0 0xfdada000 0x0 0x100>;
832 #iommu-cells = <0>;
838 reg = <0x0 0xfdb50800 0x0 0x40>;
844 #iommu-cells = <0>;
850 reg = <0x0 0xfdb60f00 0x0 0x100>;
856 #iommu-cells = <0>;
862 reg = <0x0 0xfdb70f00 0x0 0x100>;
868 #iommu-cells = <0>;
874 reg = <0x0 0xfdb90480 0x0 0x40>;
880 #iommu-cells = <0>;
886 reg = <0x0 0xfdba0800 0x0 0x40>;
892 #iommu-cells = <0>;
898 reg = <0x0 0xfdba4800 0x0 0x40>;
904 #iommu-cells = <0>;
910 reg = <0x0 0xfdba8800 0x0 0x40>;
916 #iommu-cells = <0>;
922 reg = <0x0 0xfdbac800 0x0 0x40>;
928 #iommu-cells = <0>;
934 reg = <0x0 0xfdbb0800 0x0 0x100>;
939 #iommu-cells = <0>;
946 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
954 #iommu-cells = <0>;
961 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
969 #iommu-cells = <0>;
976 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
983 #iommu-cells = <0>;
990 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>;
997 #iommu-cells = <0>;
1004 reg = <0x0 0xfdcb7f00 0x0 0x100>;
1010 #iommu-cells = <0>;
1017 reg = <0x0 0xfdcc7f00 0x0 0x100>;
1023 #iommu-cells = <0>;
1030 reg = <0x0 0xfdcd0f00 0x0 0x100>;
1036 #iommu-cells = <0>;
1042 reg = <0x0 0xfdcd8f00 0x0 0x100>;
1048 #iommu-cells = <0>;
1054 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
1059 #iommu-cells = <0>;
1066 reg = <0x0 0xfddb0000 0x0 0x1000>;
1072 #sound-dai-cells = <0>;
1078 reg = <0x0 0xfddc0000 0x0 0x1000>;
1082 dmas = <&dmac2 0>;
1086 #sound-dai-cells = <0>;
1092 reg = <0x0 0xfdde0000 0x0 0x1000>;
1098 #sound-dai-cells = <0>;
1104 reg = <0x0 0xfddf0000 0x0 0x1000>;
1112 #sound-dai-cells = <0>;
1118 reg = <0x0 0xfddfc000 0x0 0x1000>;
1126 #sound-dai-cells = <0>;
1132 reg = <0x0 0xfde08000 0x0 0x1000>;
1140 #sound-dai-cells = <0>;
1146 reg = <0x0 0xfdec0000 0x0 0x1000>;
1164 bus-range = <0x30 0x3f>;
1178 interrupt-map-mask = <0 0 0 7>;
1179 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
1180 <0 0 0 2 &pcie2x1l1_intc 1>,
1181 <0 0 0 3 &pcie2x1l1_intc 2>,
1182 <0 0 0 4 &pcie2x1l1_intc 3>;
1187 msi-map = <0x3000 &its 0x3000 0x1000>;
1192 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
1193 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
1194 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
1195 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
1197 reg = <0xa 0x40c00000 0x0 0x400000>,
1198 <0x0 0xfe180000 0x0 0x10000>;
1206 #address-cells = <0>;
1217 bus-range = <0x40 0x4f>;
1231 interrupt-map-mask = <0 0 0 7>;
1232 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
1233 <0 0 0 2 &pcie2x1l2_intc 1>,
1234 <0 0 0 3 &pcie2x1l2_intc 2>,
1235 <0 0 0 4 &pcie2x1l2_intc 3>;
1240 msi-map = <0x4000 &its 0x4000 0x1000>;
1245 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
1246 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
1247 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
1248 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
1249 reg = <0xa 0x41000000 0x0 0x400000>,
1250 <0x0 0xfe190000 0x0 0x10000>;
1258 #address-cells = <0>;
1267 reg = <0x0 0xfe1c0000 0x0 0x10000>;
1290 #address-cells = <0x1>;
1291 #size-cells = <0x0>;
1297 snps,blen = <0 0 0 0 16 8 4>;
1315 reg = <0 0xfe210000 0 0x1000>;
1323 ports-implemented = <0x1>;
1330 reg = <0 0xfe230000 0 0x1000>;
1338 ports-implemented = <0x1>;
1345 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1352 #size-cells = <0>;
1358 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1363 fifo-depth = <0x100>;
1366 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1372 reg = <0x0 0xfe2d0000 0x0 0x4000>;
1377 fifo-depth = <0x100>;
1384 reg = <0x0 0xfe2e0000 0x0 0x10000>;
1398 reg = <0x0 0xfe470000 0x0 0x1000>;
1402 dmas = <&dmac0 0>, <&dmac0 1>;
1407 pinctrl-0 = <&i2s0_lrck
1417 #sound-dai-cells = <0>;
1423 reg = <0x0 0xfe480000 0x0 0x1000>;
1432 pinctrl-0 = <&i2s1m0_lrck
1442 #sound-dai-cells = <0>;
1448 reg = <0x0 0xfe490000 0x0 0x1000>;
1452 dmas = <&dmac1 0>, <&dmac1 1>;
1455 pinctrl-0 = <&i2s2m1_lrck
1459 #sound-dai-cells = <0>;
1465 reg = <0x0 0xfe4a0000 0x0 0x1000>;
1472 pinctrl-0 = <&i2s3_lrck
1476 #sound-dai-cells = <0>;
1482 reg = <0x0 0xfe4b0000 0x0 0x1000>;
1488 pinctrl-0 = <&pdm0m0_clk
1494 #sound-dai-cells = <0>;
1500 reg = <0x0 0xfe4c0000 0x0 0x1000>;
1506 pinctrl-0 = <&pdm1m0_clk
1512 #sound-dai-cells = <0>;
1518 reg = <0x0 0xfe4d0000 0x0 0x1000>;
1523 rockchip,audio-src = <0>;
1524 rockchip,det-channel = <0>;
1525 rockchip,mode = <0>;
1526 #sound-dai-cells = <0>;
1532 reg = <0x0 0xfe4e0000 0x0 0x1000>;
1539 pinctrl-0 = <&spdif0m0_tx>;
1540 #sound-dai-cells = <0>;
1546 reg = <0x0 0xfe4f0000 0x0 0x1000>;
1553 pinctrl-0 = <&spdif1m0_tx>;
1554 #sound-dai-cells = <0>;
1560 reg = <0x0 0xfe500000 0x0 0x1000>;
1568 pinctrl-0 = <&auddsm_pins>;
1569 #sound-dai-cells = <0>;
1575 reg = <0 0xfe5a0000 0 0x100>;
1587 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
1588 <0x0 0xfe680000 0 0x100000>; /* GICR */
1594 reg = <0x0 0xfe640000 0x0 0x20000>;
1600 reg = <0x0 0xfea10000 0x0 0x4000>;
1611 reg = <0x0 0xfea30000 0x0 0x4000>;
1622 reg = <0x0 0xfea50000 0x0 0x1000>;
1629 pinctrl-0 = <&can0m0_pins>;
1637 reg = <0x0 0xfea60000 0x0 0x1000>;
1644 pinctrl-0 = <&can1m0_pins>;
1652 reg = <0x0 0xfea70000 0x0 0x1000>;
1659 pinctrl-0 = <&can2m0_pins>;
1667 reg = <0x0 0xfea80000 0x0 0x1000>;
1678 reg = <0x0 0xfea90000 0x0 0x1000>;
1683 pinctrl-0 = <&i2c1m0_xfer>;
1685 #size-cells = <0>;
1691 reg = <0x0 0xfeaa0000 0x0 0x1000>;
1696 pinctrl-0 = <&i2c2m0_xfer>;
1698 #size-cells = <0>;
1704 reg = <0x0 0xfeab0000 0x0 0x1000>;
1709 pinctrl-0 = <&i2c3m0_xfer>;
1711 #size-cells = <0>;
1717 reg = <0x0 0xfeac0000 0x0 0x1000>;
1722 pinctrl-0 = <&i2c4m0_xfer>;
1724 #size-cells = <0>;
1730 reg = <0x0 0xfead0000 0x0 0x1000>;
1735 pinctrl-0 = <&i2c5m0_xfer>;
1737 #size-cells = <0>;
1743 reg = <0x0 0xfeae0000 0x0 0x20>;
1751 reg = <0x0 0xfeaf0000 0x0 0x100>;
1760 reg = <0x0 0xfeb00000 0x0 0x1000>;
1763 #size-cells = <0>;
1769 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1777 reg = <0x0 0xfeb10000 0x0 0x1000>;
1780 #size-cells = <0>;
1786 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
1794 reg = <0x0 0xfeb20000 0x0 0x1000>;
1797 #size-cells = <0>;
1803 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1811 reg = <0x0 0xfeb30000 0x0 0x1000>;
1814 #size-cells = <0>;
1820 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
1828 reg = <0x0 0xfeb40000 0x0 0x100>;
1836 pinctrl-0 = <&uart1m0_xfer>;
1842 reg = <0x0 0xfeb50000 0x0 0x100>;
1850 pinctrl-0 = <&uart2m0_xfer>;
1856 reg = <0x0 0xfeb60000 0x0 0x100>;
1864 pinctrl-0 = <&uart3m0_xfer>;
1870 reg = <0x0 0xfeb70000 0x0 0x100>;
1878 pinctrl-0 = <&uart4m0_xfer>;
1884 reg = <0x0 0xfeb80000 0x0 0x100>;
1892 pinctrl-0 = <&uart5m0_xfer>;
1898 reg = <0x0 0xfeb90000 0x0 0x100>;
1906 pinctrl-0 = <&uart6m0_xfer>;
1912 reg = <0x0 0xfeba0000 0x0 0x100>;
1920 pinctrl-0 = <&uart7m0_xfer>;
1926 reg = <0x0 0xfebb0000 0x0 0x100>;
1934 pinctrl-0 = <&uart8m0_xfer>;
1940 reg = <0x0 0xfebc0000 0x0 0x100>;
1948 pinctrl-0 = <&uart9m0_xfer>;
1954 reg = <0x0 0xfebd0000 0x0 0x10>;
1957 pinctrl-0 = <&pwm4m0_pins>;
1965 reg = <0x0 0xfebd0010 0x0 0x10>;
1968 pinctrl-0 = <&pwm5m0_pins>;
1976 reg = <0x0 0xfebd0020 0x0 0x10>;
1979 pinctrl-0 = <&pwm6m0_pins>;
1987 reg = <0x0 0xfebd0030 0x0 0x10>;
1992 pinctrl-0 = <&pwm7m0_pins>;
2000 reg = <0x0 0xfebe0000 0x0 0x10>;
2003 pinctrl-0 = <&pwm8m0_pins>;
2011 reg = <0x0 0xfebe0010 0x0 0x10>;
2014 pinctrl-0 = <&pwm9m0_pins>;
2022 reg = <0x0 0xfebe0020 0x0 0x10>;
2025 pinctrl-0 = <&pwm10m0_pins>;
2033 reg = <0x0 0xfebe0030 0x0 0x10>;
2038 pinctrl-0 = <&pwm11m0_pins>;
2046 reg = <0x0 0xfebf0000 0x0 0x10>;
2049 pinctrl-0 = <&pwm12m0_pins>;
2057 reg = <0x0 0xfebf0010 0x0 0x10>;
2060 pinctrl-0 = <&pwm13m0_pins>;
2068 reg = <0x0 0xfebf0020 0x0 0x10>;
2071 pinctrl-0 = <&pwm14m0_pins>;
2079 reg = <0x0 0xfebf0030 0x0 0x10>;
2084 pinctrl-0 = <&pwm15m0_pins>;
2092 reg = <0x0 0xfec00000 0x0 0x400>;
2102 rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
2103 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
2105 pinctrl-0 = <&tsadc_gpio_func>;
2112 reg = <0x0 0xfec10000 0x0 0x10000>;
2125 reg = <0x0 0xfec60000 0x0 0x200>;
2139 reg = <0x0 0xfec70000 0x0 0x200>;
2152 reg = <0x0 0xfec80000 0x0 0x1000>;
2157 pinctrl-0 = <&i2c6m0_xfer>;
2159 #size-cells = <0>;
2165 reg = <0x0 0xfec90000 0x0 0x1000>;
2170 pinctrl-0 = <&i2c7m0_xfer>;
2172 #size-cells = <0>;
2178 reg = <0x0 0xfeca0000 0x0 0x1000>;
2183 pinctrl-0 = <&i2c8m0_xfer>;
2185 #size-cells = <0>;
2191 reg = <0x0 0xfecb0000 0x0 0x1000>;
2194 #size-cells = <0>;
2200 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
2208 reg = <0x0 0xfecc0000 0x0 0x400>;
2222 reg = <0x0 0xfece0000 0x0 0x200>;
2235 reg = <0x0 0xfed10000 0x0 0x4000>;
2246 reg = <0x0 0xfed60000 0x0 0x2000>;
2256 #phy-cells = <0>;
2262 reg = <0x0 0xfed80000 0x0 0x10000>;
2279 #phy-cells = <0>;
2284 #phy-cells = <0>;
2291 reg = <0x0 0xfee00000 0x0 0x100>;
2306 reg = <0x0 0xfee20000 0x0 0x100>;
2316 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
2329 reg = <0x0 0xfd8a0000 0x0 0x100>;
2335 gpio-ranges = <&pinctrl 0 0 32>;
2342 reg = <0x0 0xfec20000 0x0 0x100>;
2348 gpio-ranges = <&pinctrl 0 32 32>;
2355 reg = <0x0 0xfec30000 0x0 0x100>;
2361 gpio-ranges = <&pinctrl 0 64 32>;
2368 reg = <0x0 0xfec40000 0x0 0x100>;
2374 gpio-ranges = <&pinctrl 0 96 32>;
2381 reg = <0x0 0xfec50000 0x0 0x100>;
2387 gpio-ranges = <&pinctrl 0 128 32>;